| /* SPDX-License-Identifier: GPL-2.0-only */ | |
| /* | |
| * Copyright (C) 2018-2020 Oplus. All rights reserved. | |
| */ | |
| #ifndef __SMB1351_CHARGER_H__ | |
| #define __SMB1351_CHARGER_H__ | |
| #include <linux/power_supply.h> | |
| #ifdef CONFIG_OPLUS_CHARGER_MTK | |
| #ifdef CONFIG_OPLUS_CHARGER_6750T | |
| #include <mt-plat/charging.h> | |
| #include <mt-plat/battery_meter.h> | |
| #elif defined(CONFIG_OPLUS_CHARGER_MTK6763) | |
| #include <mt-plat/charging.h> | |
| #include <mt-plat/battery_meter.h> | |
| #else /* CONFIG_OPLUS_CHARGER_6750T */ | |
| //#include <mach/charging.h> | |
| //#include <mach/battery_meter.h> | |
| //#include <mach/mt_typedefs.h> | |
| #endif /* CONFIG_OPLUS_CHARGER_6750T */ | |
| #else /* CONFIG_OPLUS_CHARGER_MTK */ | |
| #endif /* CONFIG_OPLUS_CHARGER_MTK */ | |
| #include "../oplus_charger.h" | |
| #include <linux/power_supply.h> | |
| #include <linux/workqueue.h> | |
| #include <linux/wakelock.h> | |
| #include <linux/regulator/driver.h> | |
| #include <linux/regulator/of_regulator.h> | |
| #include <linux/regulator/machine.h> | |
| //#include <linux/qpnp/qpnp-adc.h> | |
| /* Mask/Bit helpers */ | |
| #define _SMB1351_MASK(BITS, POS) \ | |
| ((unsigned char)(((1 << (BITS)) - 1) << (POS))) | |
| #define SMB1351_MASK(LEFT_BIT_POS, RIGHT_BIT_POS) \ | |
| _SMB1351_MASK((LEFT_BIT_POS) - (RIGHT_BIT_POS) + 1, \ | |
| (RIGHT_BIT_POS)) | |
| /* Configuration registers */ | |
| #define CHG_CURRENT_CTRL_REG 0x0 | |
| #define FAST_CHG_CURRENT_MASK SMB1351_MASK(7, 4) | |
| #define AC_INPUT_CURRENT_LIMIT_MASK SMB1351_MASK(3, 0) | |
| #define REG00_SMB1351_INPUT_CURRENT_LIMIT_500MA 0 | |
| #define REG00_SMB1351_INPUT_CURRENT_LIMIT_900MA 0x02 | |
| #define REG00_SMB1351_INPUT_CURRENT_LIMIT_1200MA 0x04 | |
| #define REG00_SMB1351_INPUT_CURRENT_LIMIT_1500MA 0x06 | |
| #define REG00_SMB1351_INPUT_CURRENT_LIMIT_2000MA 0x0A | |
| #define REG00_SMB1351_INPUT_CURRENT_LIMIT_2200MA 0x0B | |
| #define CHG_OTH_CURRENT_CTRL_REG 0x1 | |
| #define PRECHG_CURRENT_MASK SMB1351_MASK(7, 5) | |
| #define ITERM_MASK SMB1351_MASK(4, 2) | |
| #define USB_2_3_MODE_SEL_BIT BIT(1) | |
| #define USB_2_3_MODE_SEL_BY_I2C 0 | |
| #define USB_2_3_MODE_SEL_BY_PIN 0x2 | |
| #define USB_5_1_CMD_POLARITY_BIT BIT(0) | |
| #define USB_CMD_POLARITY_500_1_100_0 0 | |
| #define USB_CMD_POLARITY_500_0_100_1 0x1 | |
| #define VARIOUS_FUNC_REG 0x2 | |
| #define SUSPEND_MODE_CTRL_BIT BIT(7) | |
| #define SUSPEND_MODE_CTRL_BY_PIN 0 | |
| #define SUSPEND_MODE_CTRL_BY_I2C 0x80 | |
| #define BATT_TO_SYS_POWER_CTRL_BIT BIT(6) | |
| #define MAX_SYS_VOLTAGE BIT(5) | |
| #define AICL_EN_BIT BIT(4) | |
| #define AICL_DET_TH_BIT BIT(3) | |
| #define APSD_EN_BIT BIT(2) | |
| #define BATT_OV_BIT BIT(1) | |
| #define VCHG_FUNC_BIT BIT(0) | |
| #define VFLOAT_REG 0x3 | |
| #define PRECHG_TO_FAST_VOLTAGE_CFG_MASK SMB1351_MASK(7, 6) | |
| #define VFLOAT_MASK SMB1351_MASK(5, 0) | |
| #define CHG_CTRL_REG 0x4 | |
| #define AUTO_RECHG_BIT BIT(7) | |
| #define AUTO_RECHG_ENABLE 0 | |
| #define AUTO_RECHG_DISABLE 0x80 | |
| #define ITERM_EN_BIT BIT(6) | |
| #define ITERM_ENABLE 0 | |
| #define ITERM_DISABLE 0x40 | |
| #define MAPPED_AC_INPUT_CURRENT_LIMIT_MASK SMB1351_MASK(5, 4) | |
| #define AUTO_RECHG_TH_BIT BIT(3) | |
| #define AUTO_RECHG_TH_50MV 0 | |
| #define AUTO_RECHG_TH_100MV 0x8 | |
| #define AFCV_MASK SMB1351_MASK(2, 0) | |
| #define CHG_STAT_TIMERS_CTRL_REG 0x5 | |
| #define STAT_OUTPUT_POLARITY_BIT BIT(7) | |
| #define STAT_OUTPUT_MODE_BIT BIT(6) | |
| #define STAT_OUTPUT_CTRL_BIT BIT(5) | |
| #define OTH_CHG_IL_BIT BIT(4) | |
| #define COMPLETE_CHG_TIMEOUT_MASK SMB1351_MASK(3, 2) | |
| #define PRECHG_TIMEOUT_MASK SMB1351_MASK(1, 0) | |
| #define CHG_PIN_EN_CTRL_REG 0x6 | |
| #define LED_BLINK_FUNC_BIT BIT(7) | |
| #define EN_PIN_CTRL_MASK SMB1351_MASK(6, 5) | |
| #define EN_BY_I2C_0_DISABLE 0 | |
| #define EN_BY_I2C_0_ENABLE 0x20 | |
| #define EN_BY_PIN_HIGH_ENABLE 0x40 | |
| #define EN_BY_PIN_LOW_ENABLE 0x60 | |
| #define USBCS_CTRL_BIT BIT(4) | |
| #define USBCS_CTRL_BY_I2C 0 | |
| #define USBCS_CTRL_BY_PIN 0x10 | |
| #define USBCS_INPUT_STATE_BIT BIT(3) | |
| #define CHG_ERR_BIT BIT(2) | |
| #define APSD_DONE_BIT BIT(1) | |
| #define USB_FAIL_BIT BIT(0) | |
| #define THERM_A_CTRL_REG 0x7 | |
| #define MIN_SYS_VOLTAGE_MASK SMB1351_MASK(7, 6) | |
| #define LOAD_BATT_10MA_FVC_BIT BIT(5) | |
| #define THERM_MONITOR_BIT BIT(4) | |
| #define THERM_MONITOR_EN 0 | |
| #define SOFT_COLD_TEMP_LIMIT_MASK SMB1351_MASK(3, 2) | |
| #define SOFT_HOT_TEMP_LIMIT_MASK SMB1351_MASK(1, 0) | |
| #define WDOG_SAFETY_TIMER_CTRL_REG 0x8 | |
| #define AICL_FAIL_OPTION_BIT BIT(7) | |
| #define AICL_FAIL_TO_SUSPEND 0 | |
| #define AICL_FAIL_TO_150_MA 0x80 | |
| #define WDOG_TIMEOUT_MASK SMB1351_MASK(6, 5) | |
| #define WDOG_IRQ_SAFETY_TIMER_MASK SMB1351_MASK(4, 3) | |
| #define WDOG_IRQ_SAFETY_TIMER_EN_BIT BIT(2) | |
| #define WDOG_OPTION_BIT BIT(1) | |
| #define WDOG_TIMER_EN_BIT BIT(0) | |
| #define OTG_USBIN_AICL_CTRL_REG 0x9 | |
| #define OTG_ID_PIN_CTRL_MASK SMB1351_MASK(7, 6) | |
| #define OTG_PIN_POLARITY_BIT BIT(5) | |
| #define DCIN_IC_GLITCH_FILTER_HV_ADAPTER_MASK SMB1351_MASK(4, 3) | |
| #define DCIN_IC_GLITCH_FILTER_LV_ADAPTER_BIT BIT(2) | |
| #define USBIN_AICL_CFG1_BIT BIT(1) | |
| #define USBIN_AICL_CFG0_BIT BIT(0) | |
| #define OTG_TLIM_CTRL_REG 0xA | |
| #define SWITCH_FREQ_MASK SMB1351_MASK(7, 6) | |
| #define THERM_LOOP_TEMP_SEL_MASK SMB1351_MASK(5, 4) | |
| #define OTG_OC_LIMIT_MASK SMB1351_MASK(3, 2) | |
| #define OTG_BATT_UVLO_TH_MASK SMB1351_MASK(1, 0) | |
| #define HARD_SOFT_LIMIT_CELL_TEMP_REG 0xB | |
| #define HARD_LIMIT_COLD_TEMP_ALARM_TRIP_MASK SMB1351_MASK(7, 6) | |
| #define HARD_LIMIT_HOT_TEMP_ALARM_TRIP_MASK SMB1351_MASK(5, 4) | |
| #define SOFT_LIMIT_COLD_TEMP_ALARM_TRIP_MASK SMB1351_MASK(3, 2) | |
| #define SOFT_LIMIT_HOT_TEMP_ALARM_TRIP_MASK SMB1351_MASK(1, 0) | |
| #define FAULT_INT_REG 0xC | |
| #define HOT_COLD_HARD_LIMIT_BIT BIT(7) | |
| #define HOT_COLD_SOFT_LIMIT_BIT BIT(6) | |
| #define BATT_UVLO_IN_OTG_BIT BIT(5) | |
| #define OTG_OC_BIT BIT(4) | |
| #define INPUT_OVLO_BIT BIT(3) | |
| #define INPUT_UVLO_BIT BIT(2) | |
| #define AICL_DONE_FAIL_BIT BIT(1) | |
| #define INTERNAL_OVER_TEMP_BIT BIT(0) | |
| #define STATUS_INT_REG 0xD | |
| #define CHG_OR_PRECHG_TIMEOUT_BIT BIT(7) | |
| #define RID_CHANGE_BIT BIT(6) | |
| #define BATT_OVP_BIT BIT(5) | |
| #define FAST_TERM_TAPER_RECHG_INHIBIT_BIT BIT(4) | |
| #define WDOG_TIMER_BIT BIT(3) | |
| #define POK_BIT BIT(2) | |
| #define BATT_MISSING_BIT BIT(1) | |
| #define BATT_LOW_BIT BIT(0) | |
| #define VARIOUS_FUNC_2_REG 0xE | |
| #define CHG_HOLD_OFF_TIMER_AFTER_PLUGIN_BIT BIT(7) | |
| #define CHG_INHIBIT_BIT BIT(6) | |
| #define FAST_CHG_CC_IN_BATT_SOFT_LIMIT_MODE_BIT BIT(5) | |
| #define FVCL_IN_BATT_SOFT_LIMIT_MODE_MASK SMB1351_MASK(4, 3) | |
| #define HARD_TEMP_LIMIT_BEHAVIOR_BIT BIT(2) | |
| #define PRECHG_TO_FASTCHG_BIT BIT(1) | |
| #define STAT_PIN_CONFIG_BIT BIT(0) | |
| #define FLEXCHARGER_REG 0x10 | |
| #define AFVC_IRQ_BIT BIT(7) | |
| #define CHG_CONFIG_MASK SMB1351_MASK(6, 4) | |
| #define LOW_BATT_VOLTAGE_DET_TH_MASK SMB1351_MASK(3, 0) | |
| #define VARIOUS_FUNC_3_REG 0x11 | |
| #define SAFETY_TIMER_EN_MASK SMB1351_MASK(7, 6) | |
| #define BLOCK_SUSPEND_DURING_VBATT_LOW_BIT BIT(5) | |
| #define TIMEOUT_SEL_FOR_APSD_BIT BIT(4) | |
| #define TIMEOUT_SEL_330MS BIT(4) | |
| #define SDP_SUSPEND_BIT BIT(3) | |
| #define QC_2P1_AUTO_INCREMENT_MODE_BIT BIT(2) | |
| #define QC_2P1_AUTH_ALGO_BIT BIT(1) | |
| #define DCD_EN_BIT BIT(0) | |
| #define DCD_DISABLE BIT(0) | |
| #define HVDCP_BATT_MISSING_CTRL_REG 0x12 | |
| #define HVDCP_ADAPTER_SEL_MASK SMB1351_MASK(7, 6) | |
| #define HVDCP_EN_BIT BIT(5) | |
| #define HVDCP_AUTO_INCREMENT_LIMIT_BIT BIT(4) | |
| #define BATT_MISSING_ON_INPUT_PLUGIN_BIT BIT(3) | |
| #define BATT_MISSING_2P6S_POLLER_BIT BIT(2) | |
| #define BATT_MISSING_ALGO_BIT BIT(1) | |
| #define BATT_MISSING_THERM_PIN_SOURCE_BIT BIT(0) | |
| #define PON_OPTIONS_REG 0x13 | |
| #define SYSOK_INOK_POLARITY_BIT BIT(7) | |
| #define SYSOK_OPTIONS_MASK SMB1351_MASK(6, 4) | |
| #define INPUT_MISSING_POLLER_CONFIG_BIT BIT(3) | |
| #define VBATT_LOW_DISABLED_OR_RESET_STATE_BIT BIT(2) | |
| #define QC_2P1_AUTH_ALGO_IRQ_EN_BIT BIT(0) | |
| #define OTG_MODE_POWER_OPTIONS_REG 0x14 | |
| #define ADAPTER_CONFIG_MASK SMB1351_MASK(7, 6) | |
| #define MAP_HVDCP_BIT BIT(5) | |
| #define SDP_LOW_BATT_FORCE_USB5_OVER_USB1_BIT BIT(4) | |
| #define OTG_HICCUP_MODE_BIT BIT(2) | |
| #define INPUT_CURRENT_LIMIT_MASK SMB1351_MASK(1, 0) | |
| #define CHARGER_I2C_CTRL_REG 0x15 | |
| #define FULLON_MODE_EN_BIT BIT(7) | |
| #define I2C_HS_MODE_EN_BIT BIT(6) | |
| #define SYSON_LDO_OUTPUT_SEL_BIT BIT(5) | |
| #define VBATT_TRACKING_VOLTAGE_DIFF_BIT BIT(4) | |
| #define DISABLE_AFVC_WHEN_ENTER_TAPER_BIT BIT(3) | |
| #define VCHG_IINV_BIT BIT(2) | |
| #define AFVC_OVERRIDE_BIT BIT(1) | |
| #define SYSOK_PIN_CONFIG_BIT BIT(0) | |
| #define VERSION_REG 0x2E | |
| #define VERSION_MASK BIT(1) | |
| /* Command registers */ | |
| #define CMD_I2C_REG 0x30 | |
| #define CMD_RELOAD_BIT BIT(7) | |
| #define CMD_BQ_CFG_ACCESS_BIT BIT(6) | |
| #define CMD_INPUT_LIMIT_REG 0x31 | |
| #define CMD_OVERRIDE_BIT BIT(7) | |
| #define CMD_SUSPEND_MODE_BIT BIT(6) | |
| #define CMD_INPUT_CURRENT_MODE_BIT BIT(3) | |
| #define CMD_INPUT_CURRENT_MODE_APSD 0 | |
| #define CMD_INPUT_CURRENT_MODE_CMD 0x08 | |
| #define CMD_USB_2_3_SEL_BIT BIT(2) | |
| #define CMD_USB_2_MODE 0 | |
| #define CMD_USB_3_MODE 0x4 | |
| #define CMD_USB_1_5_AC_CTRL_MASK SMB1351_MASK(1, 0) | |
| #define CMD_USB_100_MODE 0 | |
| #define CMD_USB_500_MODE 0x2 | |
| #define CMD_USB_AC_MODE 0x1 | |
| #define CMD_USB_AC_MODE_MASK BIT(0) | |
| #define CMD_CHG_REG 0x32 | |
| #define CMD_DISABLE_THERM_MONITOR_BIT BIT(4) | |
| #define CMD_TURN_OFF_STAT_PIN_BIT BIT(3) | |
| #define CMD_PRE_TO_FAST_EN_BIT BIT(2) | |
| #define CMD_CHG_EN_BIT BIT(1) | |
| #define CMD_CHG_DISABLE 0 | |
| #define CMD_CHG_ENABLE 0x2 | |
| #define CMD_OTG_EN_BIT BIT(0) | |
| #define CMD_DEAD_BATT_REG 0x33 | |
| #define CMD_STOP_DEAD_BATT_TIMER_MASK SMB1351_MASK(7, 0) | |
| #define CMD_HVDCP_REG 0x34 | |
| #define CMD_APSD_RE_RUN_BIT BIT(7) | |
| #define CMD_FORCE_HVDCP_2P0_BIT BIT(5) | |
| #define CMD_HVDCP_MODE_MASK SMB1351_MASK(5, 0) | |
| /* Status registers */ | |
| #define STATUS_0_REG 0x36 | |
| #define STATUS_AICL_BIT BIT(7) | |
| #define STATUS_INPUT_CURRENT_LIMIT_MASK SMB1351_MASK(6, 5) | |
| #define STATUS_DCIN_INPUT_CURRENT_LIMIT_MASK SMB1351_MASK(4, 0) | |
| #define STATUS_1_REG 0x37 | |
| #define STATUS_INPUT_RANGE_MASK SMB1351_MASK(7, 4) | |
| #define STATUS_INPUT_USB_BIT BIT(0) | |
| #define STATUS_2_REG 0x38 | |
| #define STATUS_FAST_CHG_BIT BIT(7) | |
| #define STATUS_HARD_LIMIT_BIT BIT(6) | |
| #define STATUS_FLOAT_VOLTAGE_MASK SMB1351_MASK(5, 0) | |
| #define STATUS_3_REG 0x39 | |
| #define STATUS_CHG_BIT BIT(7) | |
| #define STATUS_PRECHG_CURRENT_MASK SMB1351_MASK(6, 4) | |
| #define STATUS_FAST_CHG_CURRENT_MASK SMB1351_MASK(3, 0) | |
| #define STATUS_4_REG 0x3A | |
| #define STATUS_OTG_BIT BIT(7) | |
| #define STATUS_AFVC_BIT BIT(6) | |
| #define STATUS_DONE_BIT BIT(5) | |
| #define STATUS_BATT_LESS_THAN_2V_BIT BIT(4) | |
| #define STATUS_HOLD_OFF_BIT BIT(3) | |
| #define STATUS_CHG_MASK SMB1351_MASK(2, 1) | |
| #define STATUS_NO_CHARGING 0 | |
| #define STATUS_FAST_CHARGING 0x4 | |
| #define STATUS_PRE_CHARGING 0x2 | |
| #define STATUS_TAPER_CHARGING 0x6 | |
| #define STATUS_CHG_EN_STATUS_BIT BIT(0) | |
| #define STATUS_5_REG 0x3B | |
| #define STATUS_SOURCE_DETECTED_MASK SMB1351_MASK(7, 0) | |
| #define STATUS_PORT_CDP 0x80 | |
| #define STATUS_PORT_DCP 0x40 | |
| #define STATUS_PORT_OTHER 0x20 | |
| #define STATUS_PORT_SDP 0x10 | |
| #define STATUS_PORT_ACA_A 0x8 | |
| #define STATUS_PORT_ACA_B 0x4 | |
| #define STATUS_PORT_ACA_C 0x2 | |
| #define STATUS_PORT_ACA_DOCK 0x1 | |
| #define STATUS_6_REG 0x3C | |
| #define STATUS_DCD_TIMEOUT_BIT BIT(7) | |
| #define STATUS_DCD_GOOD_DG_BIT BIT(6) | |
| #define STATUS_OCD_GOOD_DG_BIT BIT(5) | |
| #define STATUS_RID_ABD_DG_BIT BIT(4) | |
| #define STATUS_RID_FLOAT_STATE_MACHINE_BIT BIT(3) | |
| #define STATUS_RID_A_STATE_MACHINE_BIT BIT(2) | |
| #define STATUS_RID_B_STATE_MACHINE_BIT BIT(1) | |
| #define STATUS_RID_C_STATE_MACHINE_BIT BIT(0) | |
| #define STATUS_7_REG 0x3D | |
| #define STATUS_HVDCP_MASK SMB1351_MASK(7, 0) | |
| #define STATUS_8_REG 0x3E | |
| #define STATUS_USNIN_HV_INPUT_SEL_BIT BIT(5) | |
| #define STATUS_USBIN_LV_UNDER_INPUT_SEL_BIT BIT(4) | |
| #define STATUS_USBIN_LV_INPUT_SEL_BIT BIT(3) | |
| /* Revision register */ | |
| #define CHG_REVISION_REG 0x3F | |
| #define GUI_REVISION_MASK SMB1351_MASK(7, 4) | |
| #define DEVICE_REVISION_MASK SMB1351_MASK(3, 0) | |
| /* IRQ status registers */ | |
| #define IRQ_A_REG 0x40 | |
| #define IRQ_HOT_HARD_BIT BIT(6) | |
| #define IRQ_COLD_HARD_BIT BIT(4) | |
| #define IRQ_HOT_SOFT_BIT BIT(2) | |
| #define IRQ_COLD_SOFT_BIT BIT(0) | |
| #define IRQ_B_REG 0x41 | |
| #define IRQ_BATT_TERMINAL_REMOVED_BIT BIT(6) | |
| #define IRQ_BATT_MISSING_BIT BIT(4) | |
| #define IRQ_LOW_BATT_VOLTAGE_BIT BIT(2) | |
| #define IRQ_INTERNAL_TEMP_LIMIT_BIT BIT(0) | |
| #define IRQ_C_REG 0x42 | |
| #define IRQ_PRE_TO_FAST_VOLTAGE_BIT BIT(6) | |
| #define IRQ_RECHG_BIT BIT(4) | |
| #define IRQ_TAPER_BIT BIT(2) | |
| #define IRQ_TERM_BIT BIT(0) | |
| #define IRQ_D_REG 0x43 | |
| #define IRQ_BATT_OV_BIT BIT(6) | |
| #define IRQ_CHG_ERROR_BIT BIT(4) | |
| #define IRQ_CHG_TIMEOUT_BIT BIT(2) | |
| #define IRQ_PRECHG_TIMEOUT_BIT BIT(0) | |
| #define IRQ_E_REG 0x44 | |
| #define IRQ_USBIN_OV_BIT BIT(6) | |
| #define IRQ_USBIN_UV_BIT BIT(4) | |
| #define IRQ_AFVC_BIT BIT(2) | |
| #define IRQ_POWER_OK_BIT BIT(0) | |
| #define IRQ_F_REG 0x45 | |
| #define IRQ_OTG_OVER_CURRENT_BIT BIT(6) | |
| #define IRQ_OTG_FAIL_BIT BIT(4) | |
| #define IRQ_RID_BIT BIT(2) | |
| #define IRQ_OTG_OC_RETRY_BIT BIT(0) | |
| #define IRQ_G_REG 0x46 | |
| #define IRQ_SOURCE_DET_BIT BIT(6) | |
| #define IRQ_AICL_DONE_BIT BIT(4) | |
| #define IRQ_AICL_FAIL_BIT BIT(2) | |
| #define IRQ_CHG_INHIBIT_BIT BIT(0) | |
| #define IRQ_H_REG 0x47 | |
| #define IRQ_IC_LIMIT_STATUS_BIT BIT(5) | |
| #define IRQ_HVDCP_2P1_STATUS_BIT BIT(4) | |
| #define IRQ_HVDCP_AUTH_DONE_BIT BIT(2) | |
| #define IRQ_WDOG_TIMEOUT_BIT BIT(0) | |
| /* constants */ | |
| #define USB2_MIN_CURRENT_MA 100 | |
| #define USB2_MAX_CURRENT_MA 500 | |
| #define USB3_MIN_CURRENT_MA 150 | |
| #define USB3_MAX_CURRENT_MA 900 | |
| #define SMB1351_IRQ_REG_COUNT 8 | |
| #define SMB1351_CHG_PRE_MIN_MA 100 | |
| #define SMB1351_CHG_FAST_MIN_MA 1000 | |
| #define SMB1351_CHG_FAST_MAX_MA 4500 | |
| #define SMB1351_CHG_PRE_SHIFT 5 | |
| #define SMB1351_CHG_FAST_SHIFT 4 | |
| #define DEFAULT_BATT_CAPACITY 50 | |
| #define DEFAULT_BATT_TEMP 250 | |
| #define SUSPEND_CURRENT_MA 2 | |
| #define CHG_ITERM_200MA 0x0 | |
| #define CHG_ITERM_300MA 0x04 | |
| #define CHG_ITERM_400MA 0x08 | |
| #define CHG_ITERM_500MA 0x0C | |
| #define CHG_ITERM_600MA 0x10 | |
| #define CHG_ITERM_700MA 0x14 | |
| #define ADC_TM_WARM_COOL_THR_ENABLE ADC_TM_HIGH_LOW_THR_ENABLE | |
| struct smb1351_regulator { | |
| struct regulator_desc rdesc; | |
| struct regulator_dev *rdev; | |
| }; | |
| enum chip_version { | |
| SMB_UNKNOWN = 0, | |
| SMB1350, | |
| SMB1351, | |
| SMB_MAX_TYPE, | |
| }; | |
| static const char *smb1351_version_str[SMB_MAX_TYPE] = { | |
| [SMB_UNKNOWN] = "Unknown", | |
| [SMB1350] = "SMB1350", | |
| [SMB1351] = "SMB1351", | |
| }; | |
| struct smb1351_charger { | |
| bool recharge_disabled; | |
| int recharge_mv; | |
| int vfloat_mv; | |
| bool iterm_disabled; | |
| int chg_present; | |
| int fake_battery_soc; | |
| bool chg_autonomous_mode; | |
| bool disable_apsd; | |
| bool using_pmic_therm; | |
| bool jeita_supported; | |
| bool battery_missing; | |
| const char *bms_psy_name; | |
| bool resume_completed; | |
| bool irq_waiting; | |
| struct delayed_work chg_remove_work; | |
| struct delayed_work hvdcp_det_work; | |
| /* status tracking */ | |
| bool batt_full; | |
| bool batt_hot; | |
| bool batt_cold; | |
| bool batt_warm; | |
| bool batt_cool; | |
| int battchg_disabled_status; | |
| int usb_suspended_status; | |
| int target_fastchg_current_max_ma; | |
| int fastchg_current_max_ma; | |
| int workaround_flags; | |
| int parallel_pin_polarity_setting; | |
| int parallel_mode; | |
| bool parallel_charger; | |
| bool parallel_charger_suspended; | |
| bool bms_controlled_charging; | |
| bool apsd_rerun; | |
| bool usbin_ov; | |
| bool chg_remove_work_scheduled; | |
| bool force_hvdcp_2p0; | |
| enum chip_version version; | |
| struct smb1351_regulator otg_vreg; | |
| struct mutex irq_complete; | |
| struct dentry *debug_root; | |
| u32 peek_poke_address; | |
| /* adc_tm parameters */ | |
| // struct qpnp_vadc_chip *vadc_dev; | |
| // struct qpnp_adc_tm_chip *adc_tm_dev; | |
| // struct qpnp_adc_tm_btm_param adc_param; | |
| /* jeita parameters */ | |
| int batt_hot_decidegc; | |
| int batt_cold_decidegc; | |
| int batt_warm_decidegc; | |
| int batt_cool_decidegc; | |
| int batt_missing_decidegc; | |
| unsigned int batt_warm_ma; | |
| unsigned int batt_warm_mv; | |
| unsigned int batt_cool_ma; | |
| unsigned int batt_cool_mv; | |
| /* pinctrl parameters */ | |
| const char *pinctrl_state_name; | |
| struct pinctrl *smb_pinctrl; | |
| struct i2c_client *client; | |
| struct device *dev; | |
| int hw_aicl_point; | |
| int sw_aicl_point; | |
| atomic_t charger_suspended; | |
| }; | |
| /* USB input charge current */ | |
| static int usb_chg_current[] = { | |
| 500, 685, 1000, 1100, 1200, 1300, 1500, 1600, | |
| 1700, 1800, 2000, 2200, 2500, 3000, | |
| }; | |
| static int fast_chg_current[] = { | |
| 1000, 1200, 1400, 1600, 1800, 2000, 2200, | |
| 2400, 2600, 2800, 3000, 3400, 3600, 3800, | |
| 4000, 4640, | |
| }; | |
| static int pre_chg_current[] = { | |
| 200, 300, 400, 500, 600, 700, | |
| }; | |
| #endif | |
| /* __OPLUS_SMB1351_H__ */ | |