| ARM Virtual Generic Interrupt Controller (VGIC) |
| =============================================== |
| |
| Device types supported: |
| KVM_DEV_TYPE_ARM_VGIC_V2 ARM Generic Interrupt Controller v2.0 |
| |
| Only one VGIC instance may be instantiated through either this API or the |
| legacy KVM_CREATE_IRQCHIP api. The created VGIC will act as the VM interrupt |
| controller, requiring emulated user-space devices to inject interrupts to the |
| VGIC instead of directly to CPUs. |
| |
| Groups: |
| KVM_DEV_ARM_VGIC_GRP_ADDR |
| Attributes: |
| KVM_VGIC_V2_ADDR_TYPE_DIST (rw, 64-bit) |
| Base address in the guest physical address space of the GIC distributor |
| register mappings. |
| |
| KVM_VGIC_V2_ADDR_TYPE_CPU (rw, 64-bit) |
| Base address in the guest physical address space of the GIC virtual cpu |
| interface register mappings. |
| |
| KVM_DEV_ARM_VGIC_GRP_DIST_REGS |
| Attributes: |
| The attr field of kvm_device_attr encodes two values: |
| bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 | |
| values: | reserved | cpu id | offset | |
| |
| All distributor regs are (rw, 32-bit) |
| |
| The offset is relative to the "Distributor base address" as defined in the |
| GICv2 specs. Getting or setting such a register has the same effect as |
| reading or writing the register on the actual hardware from the cpu |
| specified with cpu id field. Note that most distributor fields are not |
| banked, but return the same value regardless of the cpu id used to access |
| the register. |
| Limitations: |
| - Priorities are not implemented, and registers are RAZ/WI |
| Errors: |
| -ENODEV: Getting or setting this register is not yet supported |
| -EBUSY: One or more VCPUs are running |
| |
| KVM_DEV_ARM_VGIC_GRP_CPU_REGS |
| Attributes: |
| The attr field of kvm_device_attr encodes two values: |
| bits: | 63 .... 40 | 39 .. 32 | 31 .... 0 | |
| values: | reserved | cpu id | offset | |
| |
| All CPU interface regs are (rw, 32-bit) |
| |
| The offset specifies the offset from the "CPU interface base address" as |
| defined in the GICv2 specs. Getting or setting such a register has the |
| same effect as reading or writing the register on the actual hardware. |
| |
| The Active Priorities Registers APRn are implementation defined, so we set a |
| fixed format for our implementation that fits with the model of a "GICv2 |
| implementation without the security extensions" which we present to the |
| guest. This interface always exposes four register APR[0-3] describing the |
| maximum possible 128 preemption levels. The semantics of the register |
| indicate if any interrupts in a given preemption level are in the active |
| state by setting the corresponding bit. |
| |
| Thus, preemption level X has one or more active interrupts if and only if: |
| |
| APRn[X mod 32] == 0b1, where n = X / 32 |
| |
| Bits for undefined preemption levels are RAZ/WI. |
| |
| Limitations: |
| - Priorities are not implemented, and registers are RAZ/WI |
| Errors: |
| -ENODEV: Getting or setting this register is not yet supported |
| -EBUSY: One or more VCPUs are running |
| |
| KVM_DEV_ARM_VGIC_GRP_NR_IRQS |
| Attributes: |
| A value describing the number of interrupts (SGI, PPI and SPI) for |
| this GIC instance, ranging from 64 to 1024, in increments of 32. |
| |
| Errors: |
| -EINVAL: Value set is out of the expected range |
| -EBUSY: Value has already be set, or GIC has already been initialized |
| with default values. |