arch/powerpc/boot/dts/fsl/p3041si-post.dtsi - LeafOS-Devices/android_kernel_realme_mt6785 - Gitiles

 /*
  * P3041 Silicon/SoC Device Tree Source (post include)
  *
  * Copyright 2011 Freescale Semiconductor Inc.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
  *     * Redistributions of source code must retain the above copyright
  *       notice, this list of conditions and the following disclaimer.
  *     * Redistributions in binary form must reproduce the above copyright
  *       notice, this list of conditions and the following disclaimer in the
  *       documentation and/or other materials provided with the distribution.
  *     * Neither the name of Freescale Semiconductor nor the
  *       names of its contributors may be used to endorse or promote products
  *       derived from this software without specific prior written permission.
  *
  *
  * ALTERNATIVELY, this software may be distributed under the terms of the
  * GNU General Public License ("GPL") as published by the Free Software
  * Foundation, either version 2 of that License or (at your option) any
  * later version.
  *
  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */

 &lbc {
 	compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
 	interrupts = <25 2 0 0>;
 	#address-cells = <2>;
 	#size-cells = <1>;
 };

 /* controller at 0x200000 */
 &pci0 {
 	compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
 	device_type = "pci";
 	#size-cells = <2>;
 	#address-cells = <3>;
 	bus-range = <0x0 0xff>;
 	clock-frequency = <33333333>;
 	interrupts = <16 2 1 15>;
 	fsl,iommu-parent = <&pamu0>;
 	fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
 	pcie@0 {
 		reg = <0 0 0 0 0>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
 		device_type = "pci";
 		interrupts = <16 2 1 15>;
 		interrupt-map-mask = <0xf800 0 0 7>;
 		interrupt-map = <
 			/* IDSEL 0x0 */
 			0000 0 0 1 &mpic 40 1 0 0
 			0000 0 0 2 &mpic 1 1 0 0
 			0000 0 0 3 &mpic 2 1 0 0
 			0000 0 0 4 &mpic 3 1 0 0
 			>;
 	};
 };

 /* controller at 0x201000 */
 &pci1 {
 	compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
 	device_type = "pci";
 	#size-cells = <2>;
 	#address-cells = <3>;
 	bus-range = <0 0xff>;
 	clock-frequency = <33333333>;
 	interrupts = <16 2 1 14>;
 	fsl,iommu-parent = <&pamu0>;
 	fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
 	pcie@0 {
 		reg = <0 0 0 0 0>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
 		device_type = "pci";
 		interrupts = <16 2 1 14>;
 		interrupt-map-mask = <0xf800 0 0 7>;
 		interrupt-map = <
 			/* IDSEL 0x0 */
 			0000 0 0 1 &mpic 41 1 0 0
 			0000 0 0 2 &mpic 5 1 0 0
 			0000 0 0 3 &mpic 6 1 0 0
 			0000 0 0 4 &mpic 7 1 0 0
 			>;
 	};
 };

 /* controller at 0x202000 */
 &pci2 {
 	compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
 	device_type = "pci";
 	#size-cells = <2>;
 	#address-cells = <3>;
 	bus-range = <0x0 0xff>;
 	clock-frequency = <33333333>;
 	interrupts = <16 2 1 13>;
 	fsl,iommu-parent = <&pamu0>;
 	fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
 	pcie@0 {
 		reg = <0 0 0 0 0>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
 		device_type = "pci";
 		interrupts = <16 2 1 13>;
 		interrupt-map-mask = <0xf800 0 0 7>;
 		interrupt-map = <
 			/* IDSEL 0x0 */
 			0000 0 0 1 &mpic 42 1 0 0
 			0000 0 0 2 &mpic 9 1 0 0
 			0000 0 0 3 &mpic 10 1 0 0
 			0000 0 0 4 &mpic 11 1 0 0
 			>;
 	};
 };

 /* controller at 0x203000 */
 &pci3 {
 	compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
 	device_type = "pci";
 	#size-cells = <2>;
 	#address-cells = <3>;
 	bus-range = <0x0 0xff>;
 	clock-frequency = <33333333>;
 	interrupts = <16 2 1 12>;
 	pcie@0 {
 		reg = <0 0 0 0 0>;
 		#interrupt-cells = <1>;
 		#size-cells = <2>;
 		#address-cells = <3>;
 		device_type = "pci";
 		interrupts = <16 2 1 12>;
 		interrupt-map-mask = <0xf800 0 0 7>;
 		interrupt-map = <
 			/* IDSEL 0x0 */
 			0000 0 0 1 &mpic 43 1 0 0
 			0000 0 0 2 &mpic 0 1 0 0
 			0000 0 0 3 &mpic 4 1 0 0
 			0000 0 0 4 &mpic 8 1 0 0
 			>;
 	};
 };

 &rio {
 	compatible = "fsl,srio";
 	interrupts = <16 2 1 11>;
 	#address-cells = <2>;
 	#size-cells = <2>;
 	fsl,iommu-parent = <&pamu0>;
 	ranges;

 	port1 {
 		#address-cells = <2>;
 		#size-cells = <2>;
 		cell-index = <1>;
 		fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
 	};

 	port2 {
 		#address-cells = <2>;
 		#size-cells = <2>;
 		cell-index = <2>;
 		fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
 	};
 };

 &dcsr {
 	#address-cells = <1>;
 	#size-cells = <1>;
 	compatible = "fsl,dcsr", "simple-bus";

 	dcsr-epu@0 {
 		compatible = "fsl,p3041-dcsr-epu", "fsl,dcsr-epu";
 		interrupts = <52 2 0 0
 			      84 2 0 0
 			      85 2 0 0>;
 		reg = <0x0 0x1000>;
 	};
 	dcsr-npc {
 		compatible = "fsl,dcsr-npc";
 		reg = <0x1000 0x1000 0x1000000 0x8000>;
 	};
 	dcsr-nxc@2000 {
 		compatible = "fsl,dcsr-nxc";
 		reg = <0x2000 0x1000>;
 	};
 	dcsr-corenet {
 		compatible = "fsl,dcsr-corenet";
 		reg = <0x8000 0x1000 0xB0000 0x1000>;
 	};
 	dcsr-dpaa@9000 {
 		compatible = "fsl,p3041-dcsr-dpaa", "fsl,dcsr-dpaa";
 		reg = <0x9000 0x1000>;
 	};
 	dcsr-ocn@11000 {
 		compatible = "fsl,p3041-dcsr-ocn", "fsl,dcsr-ocn";
 		reg = <0x11000 0x1000>;
 	};
 	dcsr-ddr@12000 {
 		compatible = "fsl,dcsr-ddr";
 		dev-handle = <&ddr1>;
 		reg = <0x12000 0x1000>;
 	};
 	dcsr-nal@18000 {
 		compatible = "fsl,p3041-dcsr-nal", "fsl,dcsr-nal";
 		reg = <0x18000 0x1000>;
 	};
 	dcsr-rcpm@22000 {
 		compatible = "fsl,p3041-dcsr-rcpm", "fsl,dcsr-rcpm";
 		reg = <0x22000 0x1000>;
 	};
 	dcsr-cpu-sb-proxy@40000 {
 		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 		cpu-handle = <&cpu0>;
 		reg = <0x40000 0x1000>;
 	};
 	dcsr-cpu-sb-proxy@41000 {
 		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 		cpu-handle = <&cpu1>;
 		reg = <0x41000 0x1000>;
 	};
 	dcsr-cpu-sb-proxy@42000 {
 		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 		cpu-handle = <&cpu2>;
 		reg = <0x42000 0x1000>;
 	};
 	dcsr-cpu-sb-proxy@43000 {
 		compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
 		cpu-handle = <&cpu3>;
 		reg = <0x43000 0x1000>;
 	};
 };

 &soc {
 	#address-cells = <1>;
 	#size-cells = <1>;
 	device_type = "soc";
 	compatible = "simple-bus";

 	soc-sram-error {
 		compatible = "fsl,soc-sram-error";
 		interrupts = <16 2 1 29>;
 	};

 	corenet-law@0 {
 		compatible = "fsl,corenet-law";
 		reg = <0x0 0x1000>;
 		fsl,num-laws = <32>;
 	};

 	ddr1: memory-controller@8000 {
 		compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
 		reg = <0x8000 0x1000>;
 		interrupts = <16 2 1 23>;
 	};

 	cpc: l3-cache-controller@10000 {
 		compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
 		reg = <0x10000 0x1000>;
 		interrupts = <16 2 1 27>;
 	};

 	corenet-cf@18000 {
 		compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
 		reg = <0x18000 0x1000>;
 		interrupts = <16 2 1 31>;
 		fsl,ccf-num-csdids = <32>;
 		fsl,ccf-num-snoopids = <32>;
 	};

 	iommu@20000 {
 		compatible = "fsl,pamu-v1.0", "fsl,pamu";
 		reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */
 		ranges = <0 0x20000 0x4000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 		interrupts = <
 			24 2 0 0
 			16 2 1 30>;
 		fsl,portid-mapping = <0x0f000000>;

 		pamu0: pamu@0 {
 			reg = <0 0x1000>;
 			fsl,primary-cache-geometry = <32 1>;
 			fsl,secondary-cache-geometry = <128 2>;
 		};

 		pamu1: pamu@1000 {
 			reg = <0x1000 0x1000>;
 			fsl,primary-cache-geometry = <32 1>;
 			fsl,secondary-cache-geometry = <128 2>;
 		};

 		pamu2: pamu@2000 {
 			reg = <0x2000 0x1000>;
 			fsl,primary-cache-geometry = <32 1>;
 			fsl,secondary-cache-geometry = <128 2>;
 		};

 		pamu3: pamu@3000 {
 			reg = <0x3000 0x1000>;
 			fsl,primary-cache-geometry = <32 1>;
 			fsl,secondary-cache-geometry = <128 2>;
 		};
 	};

 /include/ "qoriq-mpic.dtsi"

 	guts: global-utilities@e0000 {
 		compatible = "fsl,qoriq-device-config-1.0";
 		reg = <0xe0000 0xe00>;
 		fsl,has-rstcr;
 		#sleep-cells = <1>;
 		fsl,liodn-bits = <12>;
 	};

 	pins: global-utilities@e0e00 {
 		compatible = "fsl,qoriq-pin-control-1.0";
 		reg = <0xe0e00 0x200>;
 		#sleep-cells = <2>;
 	};

 	clockgen: global-utilities@e1000 {
 		compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
 		ranges = <0x0 0xe1000 0x1000>;
 		reg = <0xe1000 0x1000>;
 		clock-frequency = <0>;
 		#address-cells = <1>;
 		#size-cells = <1>;

 		sysclk: sysclk {
 			#clock-cells = <0>;
 			compatible = "fsl,qoriq-sysclk-1.0";
 			clock-output-names = "sysclk";
 		};

 		pll0: pll0@800 {
 			#clock-cells = <1>;
 			reg = <0x800 0x4>;
 			compatible = "fsl,qoriq-core-pll-1.0";
 			clocks = <&sysclk>;
 			clock-output-names = "pll0", "pll0-div2";
 		};

 		pll1: pll1@820 {
 			#clock-cells = <1>;
 			reg = <0x820 0x4>;
 			compatible = "fsl,qoriq-core-pll-1.0";
 			clocks = <&sysclk>;
 			clock-output-names = "pll1", "pll1-div2";
 		};

 		mux0: mux0@0 {
 			#clock-cells = <0>;
 			reg = <0x0 0x4>;
 			compatible = "fsl,qoriq-core-mux-1.0";
 			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
 			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 			clock-output-names = "cmux0";
 		};

 		mux1: mux1@20 {
 			#clock-cells = <0>;
 			reg = <0x20 0x4>;
 			compatible = "fsl,qoriq-core-mux-1.0";
 			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
 			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 			clock-output-names = "cmux1";
 		};

 		mux2: mux2@40 {
 			#clock-cells = <0>;
 			reg = <0x40 0x4>;
 			compatible = "fsl,qoriq-core-mux-1.0";
 			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
 			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 			clock-output-names = "cmux2";
 		};

 		mux3: mux3@60 {
 			#clock-cells = <0>;
 			reg = <0x60 0x4>;
 			compatible = "fsl,qoriq-core-mux-1.0";
 			clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
 			clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
 			clock-output-names = "cmux3";
 		};
 	};

 	rcpm: global-utilities@e2000 {
 		compatible = "fsl,qoriq-rcpm-1.0";
 		reg = <0xe2000 0x1000>;
 		#sleep-cells = <1>;
 	};

 	sfp: sfp@e8000 {
 		compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
 		reg	   = <0xe8000 0x1000>;
 	};

 	serdes: serdes@ea000 {
 		compatible = "fsl,p3041-serdes";
 		reg	   = <0xea000 0x1000>;
 	};

 /include/ "qoriq-dma-0.dtsi"
 	dma@100300 {
 		fsl,iommu-parent = <&pamu0>;
 		fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
 	};

 /include/ "qoriq-dma-1.dtsi"
 	dma@101300 {
 		fsl,iommu-parent = <&pamu0>;
 		fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
 	};

 /include/ "qoriq-espi-0.dtsi"
 	spi@110000 {
 		fsl,espi-num-chipselects = <4>;
 	};

 /include/ "qoriq-esdhc-0.dtsi"
 	sdhc@114000 {
 		fsl,iommu-parent = <&pamu1>;
 		fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
 		sdhci,auto-cmd12;
 	};

 /include/ "qoriq-i2c-0.dtsi"
 /include/ "qoriq-i2c-1.dtsi"
 /include/ "qoriq-duart-0.dtsi"
 /include/ "qoriq-duart-1.dtsi"
 /include/ "qoriq-gpio-0.dtsi"
 /include/ "qoriq-usb2-mph-0.dtsi"
 	usb0: usb@210000 {
 		compatible = "fsl-usb2-mph-v1.6", "fsl-usb2-mph";
 		phy_type = "utmi";
 		fsl,iommu-parent = <&pamu1>;
 		fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
 		port0;
 	};

 /include/ "qoriq-usb2-dr-0.dtsi"
 	usb1: usb@211000 {
 		compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
 		fsl,iommu-parent = <&pamu1>;
 		fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
 		dr_mode = "host";
 		phy_type = "utmi";
 	};

 /include/ "qoriq-sata2-0.dtsi"
 	sata@220000 {
 		fsl,iommu-parent = <&pamu1>;
 		fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
 	};

 /include/ "qoriq-sata2-1.dtsi"
 	sata@221000 {
 		fsl,iommu-parent = <&pamu1>;
 		fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
 	};

 /include/ "qoriq-sec4.2-0.dtsi"
 crypto: crypto@300000 {
 		fsl,iommu-parent = <&pamu1>;
 	};
 };
	/*
	* P3041 Silicon/SoC Device Tree Source (post include)
	*
	* Copyright 2011 Freescale Semiconductor Inc.
	*
	* Redistribution and use in source and binary forms, with or without
	* modification, are permitted provided that the following conditions are met:
	* * Redistributions of source code must retain the above copyright
	* notice, this list of conditions and the following disclaimer.
	* * Redistributions in binary form must reproduce the above copyright
	* notice, this list of conditions and the following disclaimer in the
	* documentation and/or other materials provided with the distribution.
	* * Neither the name of Freescale Semiconductor nor the
	* names of its contributors may be used to endorse or promote products
	* derived from this software without specific prior written permission.
	*
	*
	* ALTERNATIVELY, this software may be distributed under the terms of the
	* GNU General Public License ("GPL") as published by the Free Software
	* Foundation, either version 2 of that License or (at your option) any
	* later version.
	*
	* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
	* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
	* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
	* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
	* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	*/

	&lbc {
	compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
	interrupts = <25 2 0 0>;
	#address-cells = <2>;
	#size-cells = <1>;
	};

	/* controller at 0x200000 */
	&pci0 {
	compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0x0 0xff>;
	clock-frequency = <33333333>;
	interrupts = <16 2 1 15>;
	fsl,iommu-parent = <&pamu0>;
	fsl,liodn-reg = <&guts 0x500>; /* PEX1LIODNR */
	pcie@0 {
	reg = <0 0 0 0 0>;
	#interrupt-cells = <1>;
	#size-cells = <2>;
	#address-cells = <3>;
	device_type = "pci";
	interrupts = <16 2 1 15>;
	interrupt-map-mask = <0xf800 0 0 7>;
	interrupt-map = <
	/* IDSEL 0x0 */
	0000 0 0 1 &mpic 40 1 0 0
	0000 0 0 2 &mpic 1 1 0 0
	0000 0 0 3 &mpic 2 1 0 0
	0000 0 0 4 &mpic 3 1 0 0
	>;
	};
	};

	/* controller at 0x201000 */
	&pci1 {
	compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0 0xff>;
	clock-frequency = <33333333>;
	interrupts = <16 2 1 14>;
	fsl,iommu-parent = <&pamu0>;
	fsl,liodn-reg = <&guts 0x504>; /* PEX2LIODNR */
	pcie@0 {
	reg = <0 0 0 0 0>;
	#interrupt-cells = <1>;
	#size-cells = <2>;
	#address-cells = <3>;
	device_type = "pci";
	interrupts = <16 2 1 14>;
	interrupt-map-mask = <0xf800 0 0 7>;
	interrupt-map = <
	/* IDSEL 0x0 */
	0000 0 0 1 &mpic 41 1 0 0
	0000 0 0 2 &mpic 5 1 0 0
	0000 0 0 3 &mpic 6 1 0 0
	0000 0 0 4 &mpic 7 1 0 0
	>;
	};
	};

	/* controller at 0x202000 */
	&pci2 {
	compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0x0 0xff>;
	clock-frequency = <33333333>;
	interrupts = <16 2 1 13>;
	fsl,iommu-parent = <&pamu0>;
	fsl,liodn-reg = <&guts 0x508>; /* PEX3LIODNR */
	pcie@0 {
	reg = <0 0 0 0 0>;
	#interrupt-cells = <1>;
	#size-cells = <2>;
	#address-cells = <3>;
	device_type = "pci";
	interrupts = <16 2 1 13>;
	interrupt-map-mask = <0xf800 0 0 7>;
	interrupt-map = <
	/* IDSEL 0x0 */
	0000 0 0 1 &mpic 42 1 0 0
	0000 0 0 2 &mpic 9 1 0 0
	0000 0 0 3 &mpic 10 1 0 0
	0000 0 0 4 &mpic 11 1 0 0
	>;
	};
	};

	/* controller at 0x203000 */
	&pci3 {
	compatible = "fsl,p3041-pcie", "fsl,qoriq-pcie-v2.2";
	device_type = "pci";
	#size-cells = <2>;
	#address-cells = <3>;
	bus-range = <0x0 0xff>;
	clock-frequency = <33333333>;
	interrupts = <16 2 1 12>;
	pcie@0 {
	reg = <0 0 0 0 0>;
	#interrupt-cells = <1>;
	#size-cells = <2>;
	#address-cells = <3>;
	device_type = "pci";
	interrupts = <16 2 1 12>;
	interrupt-map-mask = <0xf800 0 0 7>;
	interrupt-map = <
	/* IDSEL 0x0 */
	0000 0 0 1 &mpic 43 1 0 0
	0000 0 0 2 &mpic 0 1 0 0
	0000 0 0 3 &mpic 4 1 0 0
	0000 0 0 4 &mpic 8 1 0 0
	>;
	};
	};

	&rio {
	compatible = "fsl,srio";
	interrupts = <16 2 1 11>;
	#address-cells = <2>;
	#size-cells = <2>;
	fsl,iommu-parent = <&pamu0>;
	ranges;

	port1 {
	#address-cells = <2>;
	#size-cells = <2>;
	cell-index = <1>;
	fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
	};

	port2 {
	#address-cells = <2>;
	#size-cells = <2>;
	cell-index = <2>;
	fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
	};
	};

	&dcsr {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "fsl,dcsr", "simple-bus";

	dcsr-epu@0 {
	compatible = "fsl,p3041-dcsr-epu", "fsl,dcsr-epu";
	interrupts = <52 2 0 0
	84 2 0 0
	85 2 0 0>;
	reg = <0x0 0x1000>;
	};
	dcsr-npc {
	compatible = "fsl,dcsr-npc";
	reg = <0x1000 0x1000 0x1000000 0x8000>;
	};
	dcsr-nxc@2000 {
	compatible = "fsl,dcsr-nxc";
	reg = <0x2000 0x1000>;
	};
	dcsr-corenet {
	compatible = "fsl,dcsr-corenet";
	reg = <0x8000 0x1000 0xB0000 0x1000>;
	};
	dcsr-dpaa@9000 {
	compatible = "fsl,p3041-dcsr-dpaa", "fsl,dcsr-dpaa";
	reg = <0x9000 0x1000>;
	};
	dcsr-ocn@11000 {
	compatible = "fsl,p3041-dcsr-ocn", "fsl,dcsr-ocn";
	reg = <0x11000 0x1000>;
	};
	dcsr-ddr@12000 {
	compatible = "fsl,dcsr-ddr";
	dev-handle = <&ddr1>;
	reg = <0x12000 0x1000>;
	};
	dcsr-nal@18000 {
	compatible = "fsl,p3041-dcsr-nal", "fsl,dcsr-nal";
	reg = <0x18000 0x1000>;
	};
	dcsr-rcpm@22000 {
	compatible = "fsl,p3041-dcsr-rcpm", "fsl,dcsr-rcpm";
	reg = <0x22000 0x1000>;
	};
	dcsr-cpu-sb-proxy@40000 {
	compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
	cpu-handle = <&cpu0>;
	reg = <0x40000 0x1000>;
	};
	dcsr-cpu-sb-proxy@41000 {
	compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
	cpu-handle = <&cpu1>;
	reg = <0x41000 0x1000>;
	};
	dcsr-cpu-sb-proxy@42000 {
	compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
	cpu-handle = <&cpu2>;
	reg = <0x42000 0x1000>;
	};
	dcsr-cpu-sb-proxy@43000 {
	compatible = "fsl,dcsr-e500mc-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
	cpu-handle = <&cpu3>;
	reg = <0x43000 0x1000>;
	};
	};

	&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	device_type = "soc";
	compatible = "simple-bus";

	soc-sram-error {
	compatible = "fsl,soc-sram-error";
	interrupts = <16 2 1 29>;
	};

	corenet-law@0 {
	compatible = "fsl,corenet-law";
	reg = <0x0 0x1000>;
	fsl,num-laws = <32>;
	};

	ddr1: memory-controller@8000 {
	compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
	reg = <0x8000 0x1000>;
	interrupts = <16 2 1 23>;
	};

	cpc: l3-cache-controller@10000 {
	compatible = "fsl,p3041-l3-cache-controller", "fsl,p4080-l3-cache-controller", "cache";
	reg = <0x10000 0x1000>;
	interrupts = <16 2 1 27>;
	};

	corenet-cf@18000 {
	compatible = "fsl,corenet1-cf", "fsl,corenet-cf";
	reg = <0x18000 0x1000>;
	interrupts = <16 2 1 31>;
	fsl,ccf-num-csdids = <32>;
	fsl,ccf-num-snoopids = <32>;
	};

	iommu@20000 {
	compatible = "fsl,pamu-v1.0", "fsl,pamu";
	reg = <0x20000 0x4000>; /* for compatibility with older PAMU drivers */
	ranges = <0 0x20000 0x4000>;
	#address-cells = <1>;
	#size-cells = <1>;
	interrupts = <
	24 2 0 0
	16 2 1 30>;
	fsl,portid-mapping = <0x0f000000>;

	pamu0: pamu@0 {
	reg = <0 0x1000>;
	fsl,primary-cache-geometry = <32 1>;
	fsl,secondary-cache-geometry = <128 2>;
	};

	pamu1: pamu@1000 {
	reg = <0x1000 0x1000>;
	fsl,primary-cache-geometry = <32 1>;
	fsl,secondary-cache-geometry = <128 2>;
	};

	pamu2: pamu@2000 {
	reg = <0x2000 0x1000>;
	fsl,primary-cache-geometry = <32 1>;
	fsl,secondary-cache-geometry = <128 2>;
	};

	pamu3: pamu@3000 {
	reg = <0x3000 0x1000>;
	fsl,primary-cache-geometry = <32 1>;
	fsl,secondary-cache-geometry = <128 2>;
	};
	};

	/include/ "qoriq-mpic.dtsi"

	guts: global-utilities@e0000 {
	compatible = "fsl,qoriq-device-config-1.0";
	reg = <0xe0000 0xe00>;
	fsl,has-rstcr;
	#sleep-cells = <1>;
	fsl,liodn-bits = <12>;
	};

	pins: global-utilities@e0e00 {
	compatible = "fsl,qoriq-pin-control-1.0";
	reg = <0xe0e00 0x200>;
	#sleep-cells = <2>;
	};

	clockgen: global-utilities@e1000 {
	compatible = "fsl,p3041-clockgen", "fsl,qoriq-clockgen-1.0";
	ranges = <0x0 0xe1000 0x1000>;
	reg = <0xe1000 0x1000>;
	clock-frequency = <0>;
	#address-cells = <1>;
	#size-cells = <1>;

	sysclk: sysclk {
	#clock-cells = <0>;
	compatible = "fsl,qoriq-sysclk-1.0";
	clock-output-names = "sysclk";
	};

	pll0: pll0@800 {
	#clock-cells = <1>;
	reg = <0x800 0x4>;
	compatible = "fsl,qoriq-core-pll-1.0";
	clocks = <&sysclk>;
	clock-output-names = "pll0", "pll0-div2";
	};

	pll1: pll1@820 {
	#clock-cells = <1>;
	reg = <0x820 0x4>;
	compatible = "fsl,qoriq-core-pll-1.0";
	clocks = <&sysclk>;
	clock-output-names = "pll1", "pll1-div2";
	};

	mux0: mux0@0 {
	#clock-cells = <0>;
	reg = <0x0 0x4>;
	compatible = "fsl,qoriq-core-mux-1.0";
	clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
	clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
	clock-output-names = "cmux0";
	};

	mux1: mux1@20 {
	#clock-cells = <0>;
	reg = <0x20 0x4>;
	compatible = "fsl,qoriq-core-mux-1.0";
	clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
	clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
	clock-output-names = "cmux1";
	};

	mux2: mux2@40 {
	#clock-cells = <0>;
	reg = <0x40 0x4>;
	compatible = "fsl,qoriq-core-mux-1.0";
	clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
	clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
	clock-output-names = "cmux2";
	};

	mux3: mux3@60 {
	#clock-cells = <0>;
	reg = <0x60 0x4>;
	compatible = "fsl,qoriq-core-mux-1.0";
	clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>;
	clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2";
	clock-output-names = "cmux3";
	};
	};

	rcpm: global-utilities@e2000 {
	compatible = "fsl,qoriq-rcpm-1.0";
	reg = <0xe2000 0x1000>;
	#sleep-cells = <1>;
	};

	sfp: sfp@e8000 {
	compatible = "fsl,p3041-sfp", "fsl,qoriq-sfp-1.0";
	reg = <0xe8000 0x1000>;
	};

	serdes: serdes@ea000 {
	compatible = "fsl,p3041-serdes";
	reg = <0xea000 0x1000>;
	};

	/include/ "qoriq-dma-0.dtsi"
	dma@100300 {
	fsl,iommu-parent = <&pamu0>;
	fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
	};

	/include/ "qoriq-dma-1.dtsi"
	dma@101300 {
	fsl,iommu-parent = <&pamu0>;
	fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
	};

	/include/ "qoriq-espi-0.dtsi"
	spi@110000 {
	fsl,espi-num-chipselects = <4>;
	};

	/include/ "qoriq-esdhc-0.dtsi"
	sdhc@114000 {
	fsl,iommu-parent = <&pamu1>;
	fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
	sdhci,auto-cmd12;
	};

	/include/ "qoriq-i2c-0.dtsi"
	/include/ "qoriq-i2c-1.dtsi"
	/include/ "qoriq-duart-0.dtsi"
	/include/ "qoriq-duart-1.dtsi"
	/include/ "qoriq-gpio-0.dtsi"
	/include/ "qoriq-usb2-mph-0.dtsi"
	usb0: usb@210000 {
	compatible = "fsl-usb2-mph-v1.6", "fsl-usb2-mph";
	phy_type = "utmi";
	fsl,iommu-parent = <&pamu1>;
	fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
	port0;
	};

	/include/ "qoriq-usb2-dr-0.dtsi"
	usb1: usb@211000 {
	compatible = "fsl-usb2-dr-v1.6", "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
	fsl,iommu-parent = <&pamu1>;
	fsl,liodn-reg = <&guts 0x524>; /* USB2LIODNR */
	dr_mode = "host";
	phy_type = "utmi";
	};

	/include/ "qoriq-sata2-0.dtsi"
	sata@220000 {
	fsl,iommu-parent = <&pamu1>;
	fsl,liodn-reg = <&guts 0x550>; /* SATA1LIODNR */
	};

	/include/ "qoriq-sata2-1.dtsi"
	sata@221000 {
	fsl,iommu-parent = <&pamu1>;
	fsl,liodn-reg = <&guts 0x554>; /* SATA2LIODNR */
	};

	/include/ "qoriq-sec4.2-0.dtsi"
	crypto: crypto@300000 {
	fsl,iommu-parent = <&pamu1>;
	};
	};