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| author | 2023-06-15 14:28:46 +0000 | |
|---|---|---|
| committer | 2023-06-15 14:28:46 +0000 | |
| commit | 7225dd87f38a61ec39c0e8c88c4b088fe470d282 (patch) | |
| tree | 856c35d82928df7a93a9cec00b004be231b2c0dd | |
| parent | 5e3594fcf4330903a66f0a483807ec7d84e6dab9 (diff) | |
| parent | 121483bbbc3ead2442ba642aa0da18ce3fa958c1 (diff) | |
Merge "riscv64: enable Zbs."
| -rw-r--r-- | cc/config/riscv64_device.go | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cc/config/riscv64_device.go b/cc/config/riscv64_device.go index 77ee9774e..3bc1e69c3 100644 --- a/cc/config/riscv64_device.go +++ b/cc/config/riscv64_device.go @@ -29,14 +29,14 @@ var ( // A temporary fix for SExtWRemoval miscompilation bug. "-mllvm", "-riscv-disable-sextw-removal=true", - "-march=rv64gc_zba_zbb", + "-march=rv64gc_zba_zbb_zbs", } riscv64ArchVariantCflags = map[string][]string{} riscv64Ldflags = []string{ "-Wl,--hash-style=gnu", - "-march=rv64gc_zba_zbb", + "-march=rv64gc_zba_zbb_zbs", } riscv64Lldflags = append(riscv64Ldflags, |