/* * Copyright (C) 2012 The Android Open Source Project * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #include "../../Dalvik.h" #include "../../CompilerInternals.h" #include "X86LIR.h" #include "Codegen.h" #include /* for protection change */ namespace art { #define MAX_ASSEMBLER_RETRIES 50 X86EncodingMap EncodingMap[kX86Last] = { { kX8632BitData, kData, IS_UNARY_OP, { 0, 0, 0x00, 0, 0, 0, 0, 4 }, "data", "0x!0d" }, { kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 4 }, "int 3", "" }, { kX86Nop, kNop, IS_UNARY_OP, { 0, 0, 0x90, 0, 0, 0, 0, 0 }, "nop", "" }, #define ENCODING_MAP(opname, \ rm8_r8, rm32_r32, \ r8_rm8, r32_rm32, \ ax8_i8, ax32_i32, \ rm8_i8, rm8_i8_modrm, \ rm32_i32, rm32_i32_modrm, \ rm32_i8, rm32_i8_modrm) \ { kX86 ## opname ## 8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | SETS_CCODES, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8MR", "[!0r+!1d],!2r" }, \ { kX86 ## opname ## 8AR, kArrayReg, IS_STORE | IS_QUIN_OP | SETS_CCODES, { 0, 0, rm8_r8, 0, 0, 0, 0, 0 }, #opname "8AR", "[!0r+!1r<skeleton.prefix1 > 0) { ++size; if (entry->skeleton.prefix2 > 0) { ++size; } } ++size; // opcode if (entry->skeleton.opcode == 0x0F) { ++size; if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) { ++size; } } ++size; // modrm if (has_sib) { ++size; } if (displacement != 0) { if (entry->opcode != kX86Lea32RA) { DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), 0); } size += IS_SIMM8(displacement) ? 1 : 4; } size += entry->skeleton.immediate_bytes; return size; } int oatGetInsnSize(LIR* lir) { X86EncodingMap* entry = &EncodingMap[lir->opcode]; switch (entry->kind) { case kData: return 4; // 4 bytes of data case kNop: return lir->operands[0]; // length of nop is sole operand case kNullary: return 1; // 1 byte of opcode case kReg: // lir operands - 0: reg return computeSize(entry, 0, false); case kMem: { // lir operands - 0: base, 1: disp int base = lir->operands[0]; // SP requires a special extra SIB byte return computeSize(entry, lir->operands[1], false) + (base == rSP ? 1 : 0); } case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp return computeSize(entry, lir->operands[3], true); case kMemReg: { // lir operands - 0: base, 1: disp, 2: reg int base = lir->operands[0]; // SP requires a special extra SIB byte return computeSize(entry, lir->operands[1], false) + (base == rSP ? 1 : 0); } case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg return computeSize(entry, lir->operands[3], true); case kThreadReg: // lir operands - 0: disp, 1: reg return computeSize(entry, lir->operands[0], false); case kRegReg: return computeSize(entry, 0, false); case kRegMem: { // lir operands - 0: reg, 1: base, 2: disp int base = lir->operands[1]; return computeSize(entry, lir->operands[2], false) + (base == rSP ? 1 : 0); } case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp return computeSize(entry, lir->operands[4], true); case kRegThread: // lir operands - 0: reg, 1: disp return computeSize(entry, lir->operands[1], false); case kRegImm: { // lir operands - 0: reg, 1: immediate int reg = lir->operands[0]; // AX opcodes don't require the modrm byte. return computeSize(entry, 0, false) - (reg == rAX ? 1 : 0); } case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate CHECK_NE(lir->operands[0], static_cast(rSP)); // TODO: add extra SIB byte return computeSize(entry, lir->operands[1], false); case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate return computeSize(entry, lir->operands[3], true); case kThreadImm: // lir operands - 0: disp, 1: imm return computeSize(entry, lir->operands[0], false); case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm return computeSize(entry, 0, false); case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm CHECK_NE(lir->operands[1], static_cast(rSP)); // TODO: add extra SIB byte return computeSize(entry, lir->operands[2], false); case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm return computeSize(entry, lir->operands[4], true); case kMovRegImm: // lir operands - 0: reg, 1: immediate return 1 + entry->skeleton.immediate_bytes; case kShiftRegImm: // lir operands - 0: reg, 1: immediate // Shift by immediate one has a shorter opcode. return computeSize(entry, 0, false) - (lir->operands[1] == 1 ? 1 : 0); case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate CHECK_NE(lir->operands[0], static_cast(rSP)); // TODO: add extra SIB byte // Shift by immediate one has a shorter opcode. return computeSize(entry, lir->operands[1], false) - (lir->operands[2] == 1 ? 1 : 0); case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate // Shift by immediate one has a shorter opcode. return computeSize(entry, lir->operands[3], true) - (lir->operands[4] == 1 ? 1 : 0); case kShiftRegCl: return computeSize(entry, 0, false); case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl CHECK_NE(lir->operands[0], static_cast(rSP)); // TODO: add extra SIB byte return computeSize(entry, lir->operands[1], false); case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg return computeSize(entry, lir->operands[3], true); case kRegCond: // lir operands - 0: reg, 1: cond return computeSize(entry, 0, false); case kMemCond: // lir operands - 0: base, 1: disp, 2: cond CHECK_NE(lir->operands[0], static_cast(rSP)); // TODO: add extra SIB byte return computeSize(entry, lir->operands[1], false); case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond return computeSize(entry, lir->operands[3], true); case kJcc: case kJmp: // Jumps only return the short form length, the correct length will be assigned to LIR // flags.size during assembly. return 2; case kCall: switch(lir->opcode) { case kX86CallR: return 2; // opcode modrm case kX86CallM: // lir operands - 0: base, 1: disp return computeSize(entry, lir->operands[1], false); case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp return computeSize(entry, lir->operands[3], true); default: break; } break; default: break; } UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name; return 0; } static uint8_t modrmForDisp(int disp) { if (disp == 0) { return 0; } else if (IS_SIMM8(disp)) { return 1; } else { return 2; } } static void emitDisp(CompilationUnit* cUnit, int disp) { if (disp == 0) { return; } else if (IS_SIMM8(disp)) { cUnit->codeBuffer.push_back(disp & 0xFF); } else { cUnit->codeBuffer.push_back(disp & 0xFF); cUnit->codeBuffer.push_back((disp >> 8) & 0xFF); cUnit->codeBuffer.push_back((disp >> 16) & 0xFF); cUnit->codeBuffer.push_back((disp >> 24) & 0xFF); } } static void emitOpReg(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg) { if (entry->skeleton.prefix1 != 0) { cUnit->codeBuffer.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { cUnit->codeBuffer.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } cUnit->codeBuffer.push_back(entry->skeleton.opcode); if (entry->skeleton.opcode == 0x0F) { cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } DCHECK_LT(reg, 8); uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; cUnit->codeBuffer.push_back(modrm); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); } static void emitOpMem(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t base, int disp) { if (entry->skeleton.prefix1 != 0) { cUnit->codeBuffer.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { cUnit->codeBuffer.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } cUnit->codeBuffer.push_back(entry->skeleton.opcode); DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); DCHECK_LT(entry->skeleton.modrm_opcode, 8); DCHECK_LT(base, 8); uint8_t modrm = (modrmForDisp(disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base; cUnit->codeBuffer.push_back(modrm); emitDisp(cUnit, disp); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); } static void emitMemReg(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t base, int disp, uint8_t reg) { if (entry->skeleton.prefix1 != 0) { cUnit->codeBuffer.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { cUnit->codeBuffer.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } cUnit->codeBuffer.push_back(entry->skeleton.opcode); if (entry->skeleton.opcode == 0x0F) { cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } DCHECK_LT(reg, 8); DCHECK_LT(base, 8); uint8_t modrm = (modrmForDisp(disp) << 6) | (reg << 3) | base; cUnit->codeBuffer.push_back(modrm); if (base == rSP) { // Special SIB for SP base cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP); } emitDisp(cUnit, disp); DCHECK_EQ(0, entry->skeleton.modrm_opcode); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); } static void emitRegMem(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg, uint8_t base, int disp) { // Opcode will flip operands. emitMemReg(cUnit, entry, base, disp, reg); } static void emitRegArray(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg, uint8_t base, uint8_t index, int scale, int disp) { if (entry->skeleton.prefix1 != 0) { cUnit->codeBuffer.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { cUnit->codeBuffer.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } cUnit->codeBuffer.push_back(entry->skeleton.opcode); if (entry->skeleton.opcode == 0x0F) { cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } DCHECK_LT(reg, 8); uint8_t modrm = (modrmForDisp(disp) << 6) | (reg << 3) | rSP; cUnit->codeBuffer.push_back(modrm); DCHECK_LT(scale, 4); DCHECK_LT(index, 8); DCHECK_LT(base, 8); uint8_t sib = (scale << 6) | (index << 3) | base; cUnit->codeBuffer.push_back(sib); emitDisp(cUnit, disp); DCHECK_EQ(0, entry->skeleton.modrm_opcode); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); } static void emitRegReg(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg1, uint8_t reg2) { if (entry->skeleton.prefix1 != 0) { cUnit->codeBuffer.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { cUnit->codeBuffer.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } cUnit->codeBuffer.push_back(entry->skeleton.opcode); if (entry->skeleton.opcode == 0x0F) { cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } uint8_t modrm = (3 << 6) | (reg1 << 3) | reg2; cUnit->codeBuffer.push_back(modrm); DCHECK_EQ(0, entry->skeleton.modrm_opcode); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); } static void emitRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8_t reg, int imm) { if (entry->skeleton.prefix1 != 0) { cUnit->codeBuffer.push_back(entry->skeleton.prefix1); if (entry->skeleton.prefix2 != 0) { cUnit->codeBuffer.push_back(entry->skeleton.prefix2); } } else { DCHECK_EQ(0, entry->skeleton.prefix2); } if (reg == rAX && entry->skeleton.ax_opcode != 0) { cUnit->codeBuffer.push_back(entry->skeleton.ax_opcode); } else { cUnit->codeBuffer.push_back(entry->skeleton.opcode); if (entry->skeleton.opcode == 0x0F) { cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode1); if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode2 == 0x3A) { cUnit->codeBuffer.push_back(entry->skeleton.extra_opcode2); } else { DCHECK_EQ(0, entry->skeleton.extra_opcode2); } } else { DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); } uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg; cUnit->codeBuffer.push_back(modrm); } switch (entry->skeleton.immediate_bytes) { case 1: DCHECK(IS_SIMM8(imm)); cUnit->codeBuffer.push_back(imm & 0xFF); break; case 2: DCHECK(IS_SIMM16(imm)); cUnit->codeBuffer.push_back(imm & 0xFF); cUnit->codeBuffer.push_back((imm >> 8) & 0xFF); break; case 4: cUnit->codeBuffer.push_back(imm & 0xFF); cUnit->codeBuffer.push_back((imm >> 8) & 0xFF); cUnit->codeBuffer.push_back((imm >> 16) & 0xFF); cUnit->codeBuffer.push_back((imm >> 24) & 0xFF); break; default: LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes << ") for instruction: " << entry->name; break; } } /* * Assemble the LIR into binary instruction format. Note that we may * discover that pc-relative displacements may not fit the selected * instruction. In those cases we will try to substitute a new code * sequence or request that the trace be shortened and retried. */ AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit, intptr_t startAddr) { LIR *lir; AssemblerStatus res = kSuccess; // Assume success for (lir = (LIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) { if (lir->opcode < 0) { continue; } if (lir->flags.isNop) { continue; } if (lir->flags.pcRelFixup) { UNIMPLEMENTED(WARNING) << "PC relative fix up"; } /* * If one of the pc-relative instructions expanded we'll have * to make another pass. Don't bother to fully assemble the * instruction. */ if (res != kSuccess) { continue; } const X86EncodingMap *entry = &EncodingMap[lir->opcode]; switch(entry->kind) { case kData: // 4 bytes of data cUnit->codeBuffer.push_back(lir->operands[0]); break; case kNullary: // 1 byte of opcode DCHECK_EQ(0, entry->skeleton.prefix1); DCHECK_EQ(0, entry->skeleton.prefix2); cUnit->codeBuffer.push_back(entry->skeleton.opcode); DCHECK_EQ(0, entry->skeleton.extra_opcode1); DCHECK_EQ(0, entry->skeleton.extra_opcode2); DCHECK_EQ(0, entry->skeleton.modrm_opcode); DCHECK_EQ(0, entry->skeleton.ax_opcode); DCHECK_EQ(0, entry->skeleton.immediate_bytes); break; case kReg: // lir operands - 0: reg emitOpReg(cUnit, entry, lir->operands[0]); break; case kMem: // lir operands - 0: base, 1: disp emitOpMem(cUnit, entry, lir->operands[0], lir->operands[1]); break; case kMemReg: // lir operands - 0: base, 1: disp, 2: reg emitMemReg(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]); break; case kRegMem: // lir operands - 0: reg, 1: base, 2: disp emitRegMem(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2]); break; case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp emitRegArray(cUnit, entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3], lir->operands[4]); break; case kRegReg: // lir operands - 0: reg1, 1: reg2 emitRegReg(cUnit, entry, lir->operands[0], lir->operands[1]); break; case kRegImm: // lir operands - 0: reg, 1: immediate emitRegImm(cUnit, entry, lir->operands[0], lir->operands[1]); break; default: UNIMPLEMENTED(FATAL) << "Unimplemented encoding for: " << entry->name; break; } } return res; } /* * Target-dependent offset assignment. * independent. */ int oatAssignInsnOffsets(CompilationUnit* cUnit) { LIR* x86LIR; int offset = 0; for (x86LIR = (LIR *) cUnit->firstLIRInsn; x86LIR; x86LIR = NEXT_LIR(x86LIR)) { x86LIR->offset = offset; if (x86LIR->opcode >= 0) { if (!x86LIR->flags.isNop) { offset += x86LIR->flags.size; } } else if (x86LIR->opcode == kPseudoPseudoAlign4) { if (offset & 0x2) { offset += 2; x86LIR->operands[0] = 1; } else { x86LIR->operands[0] = 0; } } /* Pseudo opcodes don't consume space */ } return offset; } } // namespace art