/* * Copyright (C) 2011 The Android Open Source Project * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef ART_SRC_COMPILER_CODEGEN_ARM_ARMLIR_H_ #define ART_SRC_COMPILER_CODEGEN_ARM_ARMLIR_H_ #include "../../Dalvik.h" #include "../../CompilerInternals.h" namespace art { // Set to 1 to measure cost of suspend check #define NO_SUSPEND 0 /* * Runtime register usage conventions. * * r0-r3: Argument registers in both Dalvik and C/C++ conventions. * However, for Dalvik->Dalvik calls we'll pass the target's Method* * pointer in r0 as a hidden arg0. Otherwise used as codegen scratch * registers. * r0-r1: As in C/C++ r0 is 32-bit return register and r0/r1 is 64-bit * r4 : (rSUSPEND) is reserved (suspend check/debugger assist) * r5 : Callee save (promotion target) * r6 : Callee save (promotion target) * r7 : Callee save (promotion target) * r8 : Callee save (promotion target) * r9 : (rSELF) is reserved (pointer to thread-local storage) * r10 : Callee save (promotion target) * r11 : Callee save (promotion target) * r12 : Scratch, may be trashed by linkage stubs * r13 : (sp) is reserved * r14 : (lr) is reserved * r15 : (pc) is reserved * * 5 core temps that codegen can use (r0, r1, r2, r3, r12) * 7 core registers that can be used for promotion * * Floating pointer registers * s0-s31 * d0-d15, where d0={s0,s1}, d1={s2,s3}, ... , d15={s30,s31} * * s16-s31 (d8-d15) preserved across C calls * s0-s15 (d0-d7) trashed across C calls * * s0-s15/d0-d7 used as codegen temp/scratch * s16-s31/d8-d31 can be used for promotion. * * Calling convention * o On a call to a Dalvik method, pass target's Method* in r0 * o r1-r3 will be used for up to the first 3 words of arguments * o Arguments past the first 3 words will be placed in appropriate * out slots by the caller. * o If a 64-bit argument would span the register/memory argument * boundary, it will instead be fully passed in the frame. * o Maintain a 16-byte stack alignment * * Stack frame diagram (stack grows down, higher addresses at top): * * +------------------------+ * | IN[ins-1] | {Note: resides in caller's frame} * | . | * | IN[0] | * | caller's Method* | * +========================+ {Note: start of callee's frame} * | spill region | {variable sized - will include lr if non-leaf.} * +------------------------+ * | ...filler word... | {Note: used as 2nd word of V[locals-1] if long] * +------------------------+ * | V[locals-1] | * | V[locals-2] | * | . | * | . | * | V[1] | * | V[0] | * +------------------------+ * | 0 to 3 words padding | * +------------------------+ * | OUT[outs-1] | * | OUT[outs-2] | * | . | * | OUT[0] | * | curMethod* | <<== sp w/ 16-byte alignment * +========================+ */ /* Offset to distingish FP regs */ #define FP_REG_OFFSET 32 /* Offset to distinguish DP FP regs */ #define FP_DOUBLE 64 /* First FP callee save */ #define FP_CALLEE_SAVE_BASE 16 /* Reg types */ #define REGTYPE(x) (x & (FP_REG_OFFSET | FP_DOUBLE)) #define FPREG(x) ((x & FP_REG_OFFSET) == FP_REG_OFFSET) #define LOWREG(x) ((x & 0x7) == x) #define DOUBLEREG(x) ((x & FP_DOUBLE) == FP_DOUBLE) #define SINGLEREG(x) (FPREG(x) && !DOUBLEREG(x)) /* * Note: the low register of a floating point pair is sufficient to * create the name of a double, but require both names to be passed to * allow for asserts to verify that the pair is consecutive if significant * rework is done in this area. Also, it is a good reminder in the calling * code that reg locations always describe doubles as a pair of singles. */ #define S2D(x,y) ((x) | FP_DOUBLE) /* Mask to strip off fp flags */ #define FP_REG_MASK (FP_REG_OFFSET-1) /* non-existent Dalvik register */ #define vNone (-1) /* non-existant physical register */ #define rNone (-1) /* RegisterLocation templates return values (r0, or r0/r1) */ #define LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 1, r0, INVALID_REG,\ INVALID_SREG} #define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG} enum ResourceEncodingPos { kGPReg0 = 0, kRegSP = 13, kRegLR = 14, kRegPC = 15, kFPReg0 = 16, kFPReg16 = 32, kRegEnd = 48, kCCode = kRegEnd, kFPStatus, // FP status word // The following four bits are for memory disambiguation kDalvikReg, // 1 Dalvik Frame (can be fully disambiguated) kLiteral, // 2 Literal pool (can be fully disambiguated) kHeapRef, // 3 Somewhere on the heap (alias with any other heap) kMustNotAlias, // 4 Guaranteed to be non-alias (eg *(r6+x)) }; #define ENCODE_REG_LIST(N) ((u8) N) #define ENCODE_REG_SP (1ULL << kRegSP) #define ENCODE_REG_LR (1ULL << kRegLR) #define ENCODE_REG_PC (1ULL << kRegPC) #define ENCODE_CCODE (1ULL << kCCode) #define ENCODE_FP_STATUS (1ULL << kFPStatus) #define ENCODE_REG_FPCS_LIST(N) ((u8)N << kFPReg16) /* Abstract memory locations */ #define ENCODE_DALVIK_REG (1ULL << kDalvikReg) #define ENCODE_LITERAL (1ULL << kLiteral) #define ENCODE_HEAP_REF (1ULL << kHeapRef) #define ENCODE_MUST_NOT_ALIAS (1ULL << kMustNotAlias) #define ENCODE_ALL (~0ULL) #define ENCODE_MEM (ENCODE_DALVIK_REG | ENCODE_LITERAL | \ ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS) #define DECODE_ALIAS_INFO_REG(X) (X & 0xffff) #define DECODE_ALIAS_INFO_WIDE(X) ((X & 0x80000000) ? 1 : 0) /* * Annotate special-purpose core registers: * - VM: r6SELF * - ARM architecture: r13sp, r14lr, and r15pc * * rPC, rFP, and rSELF are for architecture-independent code to use. */ enum NativeRegisterPool { r0 = 0, r1 = 1, r2 = 2, r3 = 3, rSUSPEND = 4, r5 = 5, r6 = 6, r7 = 7, r8 = 8, rSELF = 9, r10 = 10, r11 = 11, r12 = 12, r13sp = 13, rSP = 13, r14lr = 14, rLR = 14, r15pc = 15, rPC = 15, fr0 = 0 + FP_REG_OFFSET, fr1 = 1 + FP_REG_OFFSET, fr2 = 2 + FP_REG_OFFSET, fr3 = 3 + FP_REG_OFFSET, fr4 = 4 + FP_REG_OFFSET, fr5 = 5 + FP_REG_OFFSET, fr6 = 6 + FP_REG_OFFSET, fr7 = 7 + FP_REG_OFFSET, fr8 = 8 + FP_REG_OFFSET, fr9 = 9 + FP_REG_OFFSET, fr10 = 10 + FP_REG_OFFSET, fr11 = 11 + FP_REG_OFFSET, fr12 = 12 + FP_REG_OFFSET, fr13 = 13 + FP_REG_OFFSET, fr14 = 14 + FP_REG_OFFSET, fr15 = 15 + FP_REG_OFFSET, fr16 = 16 + FP_REG_OFFSET, fr17 = 17 + FP_REG_OFFSET, fr18 = 18 + FP_REG_OFFSET, fr19 = 19 + FP_REG_OFFSET, fr20 = 20 + FP_REG_OFFSET, fr21 = 21 + FP_REG_OFFSET, fr22 = 22 + FP_REG_OFFSET, fr23 = 23 + FP_REG_OFFSET, fr24 = 24 + FP_REG_OFFSET, fr25 = 25 + FP_REG_OFFSET, fr26 = 26 + FP_REG_OFFSET, fr27 = 27 + FP_REG_OFFSET, fr28 = 28 + FP_REG_OFFSET, fr29 = 29 + FP_REG_OFFSET, fr30 = 30 + FP_REG_OFFSET, fr31 = 31 + FP_REG_OFFSET, dr0 = fr0 + FP_DOUBLE, dr1 = fr2 + FP_DOUBLE, dr2 = fr4 + FP_DOUBLE, dr3 = fr6 + FP_DOUBLE, dr4 = fr8 + FP_DOUBLE, dr5 = fr10 + FP_DOUBLE, dr6 = fr12 + FP_DOUBLE, dr7 = fr14 + FP_DOUBLE, dr8 = fr16 + FP_DOUBLE, dr9 = fr18 + FP_DOUBLE, dr10 = fr20 + FP_DOUBLE, dr11 = fr22 + FP_DOUBLE, dr12 = fr24 + FP_DOUBLE, dr13 = fr26 + FP_DOUBLE, dr14 = fr28 + FP_DOUBLE, dr15 = fr30 + FP_DOUBLE, }; /* Target-independent aliases */ #define rARG0 r0 #define rARG1 r1 #define rARG2 r2 #define rARG3 r3 #define rRET0 r0 #define rRET1 r1 #define rINVOKE_TGT rLR /* Shift encodings */ enum ArmShiftEncodings { kArmLsl = 0x0, kArmLsr = 0x1, kArmAsr = 0x2, kArmRor = 0x3 }; /* Thumb condition encodings */ enum ArmConditionCode { kArmCondEq = 0x0, /* 0000 */ kArmCondNe = 0x1, /* 0001 */ kArmCondCs = 0x2, /* 0010 */ kArmCondCc = 0x3, /* 0011 */ kArmCondMi = 0x4, /* 0100 */ kArmCondPl = 0x5, /* 0101 */ kArmCondVs = 0x6, /* 0110 */ kArmCondVc = 0x7, /* 0111 */ kArmCondHi = 0x8, /* 1000 */ kArmCondLs = 0x9, /* 1001 */ kArmCondGe = 0xa, /* 1010 */ kArmCondLt = 0xb, /* 1011 */ kArmCondGt = 0xc, /* 1100 */ kArmCondLe = 0xd, /* 1101 */ kArmCondAl = 0xe, /* 1110 */ kArmCondNv = 0xf, /* 1111 */ }; #define isPseudoOpcode(opcode) ((int)(opcode) < 0) /* * The following enum defines the list of supported Thumb instructions by the * assembler. Their corresponding EncodingMap positions will be defined in * Assemble.cc. */ enum ArmOpcode { kPseudoSuspendTarget = -15, kPseudoThrowTarget = -14, kPseudoCaseLabel = -13, kPseudoMethodEntry = -12, kPseudoMethodExit = -11, kPseudoBarrier = -10, kPseudoExtended = -9, kPseudoSSARep = -8, kPseudoEntryBlock = -7, kPseudoExitBlock = -6, kPseudoTargetLabel = -5, kPseudoDalvikByteCodeBoundary = -4, kPseudoPseudoAlign4 = -3, kPseudoEHBlockLabel = -2, kPseudoNormalBlockLabel = -1, /************************************************************************/ kArm16BitData, /* DATA [0] rd[15..0] */ kThumbAdcRR, /* adc [0100000101] rm[5..3] rd[2..0] */ kThumbAddRRI3, /* add(1) [0001110] imm_3[8..6] rn[5..3] rd[2..0]*/ kThumbAddRI8, /* add(2) [00110] rd[10..8] imm_8[7..0] */ kThumbAddRRR, /* add(3) [0001100] rm[8..6] rn[5..3] rd[2..0] */ kThumbAddRRLH, /* add(4) [01000100] H12[01] rm[5..3] rd[2..0] */ kThumbAddRRHL, /* add(4) [01001000] H12[10] rm[5..3] rd[2..0] */ kThumbAddRRHH, /* add(4) [01001100] H12[11] rm[5..3] rd[2..0] */ kThumbAddPcRel, /* add(5) [10100] rd[10..8] imm_8[7..0] */ kThumbAddSpRel, /* add(6) [10101] rd[10..8] imm_8[7..0] */ kThumbAddSpI7, /* add(7) [101100000] imm_7[6..0] */ kThumbAndRR, /* and [0100000000] rm[5..3] rd[2..0] */ kThumbAsrRRI5, /* asr(1) [00010] imm_5[10..6] rm[5..3] rd[2..0] */ kThumbAsrRR, /* asr(2) [0100000100] rs[5..3] rd[2..0] */ kThumbBCond, /* b(1) [1101] cond[11..8] offset_8[7..0] */ kThumbBUncond, /* b(2) [11100] offset_11[10..0] */ kThumbBicRR, /* bic [0100001110] rm[5..3] rd[2..0] */ kThumbBkpt, /* bkpt [10111110] imm_8[7..0] */ kThumbBlx1, /* blx(1) [111] H[10] offset_11[10..0] */ kThumbBlx2, /* blx(1) [111] H[01] offset_11[10..0] */ kThumbBl1, /* blx(1) [111] H[10] offset_11[10..0] */ kThumbBl2, /* blx(1) [111] H[11] offset_11[10..0] */ kThumbBlxR, /* blx(2) [010001111] rm[6..3] [000] */ kThumbBx, /* bx [010001110] H2[6..6] rm[5..3] SBZ[000] */ kThumbCmnRR, /* cmn [0100001011] rm[5..3] rd[2..0] */ kThumbCmpRI8, /* cmp(1) [00101] rn[10..8] imm_8[7..0] */ kThumbCmpRR, /* cmp(2) [0100001010] rm[5..3] rd[2..0] */ kThumbCmpLH, /* cmp(3) [01000101] H12[01] rm[5..3] rd[2..0] */ kThumbCmpHL, /* cmp(3) [01000110] H12[10] rm[5..3] rd[2..0] */ kThumbCmpHH, /* cmp(3) [01000111] H12[11] rm[5..3] rd[2..0] */ kThumbEorRR, /* eor [0100000001] rm[5..3] rd[2..0] */ kThumbLdmia, /* ldmia [11001] rn[10..8] reglist [7..0] */ kThumbLdrRRI5, /* ldr(1) [01101] imm_5[10..6] rn[5..3] rd[2..0] */ kThumbLdrRRR, /* ldr(2) [0101100] rm[8..6] rn[5..3] rd[2..0] */ kThumbLdrPcRel, /* ldr(3) [01001] rd[10..8] imm_8[7..0] */ kThumbLdrSpRel, /* ldr(4) [10011] rd[10..8] imm_8[7..0] */ kThumbLdrbRRI5, /* ldrb(1) [01111] imm_5[10..6] rn[5..3] rd[2..0] */ kThumbLdrbRRR, /* ldrb(2) [0101110] rm[8..6] rn[5..3] rd[2..0] */ kThumbLdrhRRI5, /* ldrh(1) [10001] imm_5[10..6] rn[5..3] rd[2..0] */ kThumbLdrhRRR, /* ldrh(2) [0101101] rm[8..6] rn[5..3] rd[2..0] */ kThumbLdrsbRRR, /* ldrsb [0101011] rm[8..6] rn[5..3] rd[2..0] */ kThumbLdrshRRR, /* ldrsh [0101111] rm[8..6] rn[5..3] rd[2..0] */ kThumbLslRRI5, /* lsl(1) [00000] imm_5[10..6] rm[5..3] rd[2..0] */ kThumbLslRR, /* lsl(2) [0100000010] rs[5..3] rd[2..0] */ kThumbLsrRRI5, /* lsr(1) [00001] imm_5[10..6] rm[5..3] rd[2..0] */ kThumbLsrRR, /* lsr(2) [0100000011] rs[5..3] rd[2..0] */ kThumbMovImm, /* mov(1) [00100] rd[10..8] imm_8[7..0] */ kThumbMovRR, /* mov(2) [0001110000] rn[5..3] rd[2..0] */ kThumbMovRR_H2H, /* mov(3) [01000111] H12[11] rm[5..3] rd[2..0] */ kThumbMovRR_H2L, /* mov(3) [01000110] H12[01] rm[5..3] rd[2..0] */ kThumbMovRR_L2H, /* mov(3) [01000101] H12[10] rm[5..3] rd[2..0] */ kThumbMul, /* mul [0100001101] rm[5..3] rd[2..0] */ kThumbMvn, /* mvn [0100001111] rm[5..3] rd[2..0] */ kThumbNeg, /* neg [0100001001] rm[5..3] rd[2..0] */ kThumbOrr, /* orr [0100001100] rm[5..3] rd[2..0] */ kThumbPop, /* pop [1011110] r[8..8] rl[7..0] */ kThumbPush, /* push [1011010] r[8..8] rl[7..0] */ kThumbRorRR, /* ror [0100000111] rs[5..3] rd[2..0] */ kThumbSbc, /* sbc [0100000110] rm[5..3] rd[2..0] */ kThumbStmia, /* stmia [11000] rn[10..8] reglist [7.. 0] */ kThumbStrRRI5, /* str(1) [01100] imm_5[10..6] rn[5..3] rd[2..0] */ kThumbStrRRR, /* str(2) [0101000] rm[8..6] rn[5..3] rd[2..0] */ kThumbStrSpRel, /* str(3) [10010] rd[10..8] imm_8[7..0] */ kThumbStrbRRI5, /* strb(1) [01110] imm_5[10..6] rn[5..3] rd[2..0] */ kThumbStrbRRR, /* strb(2) [0101010] rm[8..6] rn[5..3] rd[2..0] */ kThumbStrhRRI5, /* strh(1) [10000] imm_5[10..6] rn[5..3] rd[2..0] */ kThumbStrhRRR, /* strh(2) [0101001] rm[8..6] rn[5..3] rd[2..0] */ kThumbSubRRI3, /* sub(1) [0001111] imm_3[8..6] rn[5..3] rd[2..0]*/ kThumbSubRI8, /* sub(2) [00111] rd[10..8] imm_8[7..0] */ kThumbSubRRR, /* sub(3) [0001101] rm[8..6] rn[5..3] rd[2..0] */ kThumbSubSpI7, /* sub(4) [101100001] imm_7[6..0] */ kThumbSwi, /* swi [11011111] imm_8[7..0] */ kThumbTst, /* tst [0100001000] rm[5..3] rn[2..0] */ kThumb2Vldrs, /* vldr low sx [111011011001] rn[19..16] rd[15-12] [1010] imm_8[7..0] */ kThumb2Vldrd, /* vldr low dx [111011011001] rn[19..16] rd[15-12] [1011] imm_8[7..0] */ kThumb2Vmuls, /* vmul vd, vn, vm [111011100010] rn[19..16] rd[15-12] [10100000] rm[3..0] */ kThumb2Vmuld, /* vmul vd, vn, vm [111011100010] rn[19..16] rd[15-12] [10110000] rm[3..0] */ kThumb2Vstrs, /* vstr low sx [111011011000] rn[19..16] rd[15-12] [1010] imm_8[7..0] */ kThumb2Vstrd, /* vstr low dx [111011011000] rn[19..16] rd[15-12] [1011] imm_8[7..0] */ kThumb2Vsubs, /* vsub vd, vn, vm [111011100011] rn[19..16] rd[15-12] [10100040] rm[3..0] */ kThumb2Vsubd, /* vsub vd, vn, vm [111011100011] rn[19..16] rd[15-12] [10110040] rm[3..0] */ kThumb2Vadds, /* vadd vd, vn, vm [111011100011] rn[19..16] rd[15-12] [10100000] rm[3..0] */ kThumb2Vaddd, /* vadd vd, vn, vm [111011100011] rn[19..16] rd[15-12] [10110000] rm[3..0] */ kThumb2Vdivs, /* vdiv vd, vn, vm [111011101000] rn[19..16] rd[15-12] [10100000] rm[3..0] */ kThumb2Vdivd, /* vdiv vd, vn, vm [111011101000] rn[19..16] rd[15-12] [10110000] rm[3..0] */ kThumb2VcvtIF, /* vcvt.F32 vd, vm [1110111010111000] vd[15..12] [10101100] vm[3..0] */ kThumb2VcvtID, /* vcvt.F64 vd, vm [1110111010111000] vd[15..12] [10111100] vm[3..0] */ kThumb2VcvtFI, /* vcvt.S32.F32 vd, vm [1110111010111101] vd[15..12] [10101100] vm[3..0] */ kThumb2VcvtDI, /* vcvt.S32.F32 vd, vm [1110111010111101] vd[15..12] [10111100] vm[3..0] */ kThumb2VcvtFd, /* vcvt.F64.F32 vd, vm [1110111010110111] vd[15..12] [10101100] vm[3..0] */ kThumb2VcvtDF, /* vcvt.F32.F64 vd, vm [1110111010110111] vd[15..12] [10111100] vm[3..0] */ kThumb2Vsqrts, /* vsqrt.f32 vd, vm [1110111010110001] vd[15..12] [10101100] vm[3..0] */ kThumb2Vsqrtd, /* vsqrt.f64 vd, vm [1110111010110001] vd[15..12] [10111100] vm[3..0] */ kThumb2MovImmShift, /* mov(T2) rd, # [11110] i [00001001111] imm3 rd[11..8] imm8 */ kThumb2MovImm16, /* mov(T3) rd, # [11110] i [0010100] imm4 [0] imm3 rd[11..8] imm8 */ kThumb2StrRRI12, /* str(Imm,T3) rd,[rn,#imm12] [111110001100] rn[19..16] rt[15..12] imm12[11..0] */ kThumb2LdrRRI12, /* str(Imm,T3) rd,[rn,#imm12] [111110001100] rn[19..16] rt[15..12] imm12[11..0] */ kThumb2StrRRI8Predec, /* str(Imm,T4) rd,[rn,#-imm8] [111110000100] rn[19..16] rt[15..12] [1100] imm[7..0]*/ kThumb2LdrRRI8Predec, /* ldr(Imm,T4) rd,[rn,#-imm8] [111110000101] rn[19..16] rt[15..12] [1100] imm[7..0]*/ kThumb2Cbnz, /* cbnz rd,