/* * Copyright (C) 2014 The Android Open Source Project * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. */ #ifndef ART_COMPILER_UTILS_ARM_ASSEMBLER_THUMB2_H_ #define ART_COMPILER_UTILS_ARM_ASSEMBLER_THUMB2_H_ #include #include #include #include "base/arena_containers.h" #include "base/array_ref.h" #include "base/logging.h" #include "constants_arm.h" #include "utils/arm/managed_register_arm.h" #include "utils/arm/assembler_arm.h" #include "offsets.h" namespace art { namespace arm { class Thumb2Assembler FINAL : public ArmAssembler { public: explicit Thumb2Assembler(ArenaAllocator* arena, bool can_relocate_branches = true) : ArmAssembler(arena), can_relocate_branches_(can_relocate_branches), force_32bit_(false), it_cond_index_(kNoItCondition), next_condition_(AL), fixups_(arena->Adapter(kArenaAllocAssembler)), fixup_dependents_(arena->Adapter(kArenaAllocAssembler)), literals_(arena->Adapter(kArenaAllocAssembler)), literal64_dedupe_map_(std::less(), arena->Adapter(kArenaAllocAssembler)), jump_tables_(arena->Adapter(kArenaAllocAssembler)), last_position_adjustment_(0u), last_old_position_(0u), last_fixup_id_(0u) { cfi().DelayEmittingAdvancePCs(); } virtual ~Thumb2Assembler() { } bool IsThumb() const OVERRIDE { return true; } bool IsForced32Bit() const { return force_32bit_; } bool CanRelocateBranches() const { return can_relocate_branches_; } void FinalizeCode() OVERRIDE; // Data-processing instructions. virtual void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void rsc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; void tst(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; void teq(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; void cmp(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; void cmn(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; virtual void orr(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void orn(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void mov(Register rd, const ShifterOperand& so, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void bic(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void mvn(Register rd, const ShifterOperand& so, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; // Miscellaneous data-processing instructions. void clz(Register rd, Register rm, Condition cond = AL) OVERRIDE; void movw(Register rd, uint16_t imm16, Condition cond = AL) OVERRIDE; void movt(Register rd, uint16_t imm16, Condition cond = AL) OVERRIDE; void rbit(Register rd, Register rm, Condition cond = AL) OVERRIDE; void rev(Register rd, Register rm, Condition cond = AL) OVERRIDE; void rev16(Register rd, Register rm, Condition cond = AL) OVERRIDE; void revsh(Register rd, Register rm, Condition cond = AL) OVERRIDE; // Multiply instructions. void mul(Register rd, Register rn, Register rm, Condition cond = AL) OVERRIDE; void mla(Register rd, Register rn, Register rm, Register ra, Condition cond = AL) OVERRIDE; void mls(Register rd, Register rn, Register rm, Register ra, Condition cond = AL) OVERRIDE; void smull(Register rd_lo, Register rd_hi, Register rn, Register rm, Condition cond = AL) OVERRIDE; void umull(Register rd_lo, Register rd_hi, Register rn, Register rm, Condition cond = AL) OVERRIDE; void sdiv(Register rd, Register rn, Register rm, Condition cond = AL) OVERRIDE; void udiv(Register rd, Register rn, Register rm, Condition cond = AL) OVERRIDE; // Bit field extract instructions. void sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond = AL) OVERRIDE; void ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond = AL) OVERRIDE; // Load/store instructions. void ldr(Register rd, const Address& ad, Condition cond = AL) OVERRIDE; void str(Register rd, const Address& ad, Condition cond = AL) OVERRIDE; void ldrb(Register rd, const Address& ad, Condition cond = AL) OVERRIDE; void strb(Register rd, const Address& ad, Condition cond = AL) OVERRIDE; void ldrh(Register rd, const Address& ad, Condition cond = AL) OVERRIDE; void strh(Register rd, const Address& ad, Condition cond = AL) OVERRIDE; void ldrsb(Register rd, const Address& ad, Condition cond = AL) OVERRIDE; void ldrsh(Register rd, const Address& ad, Condition cond = AL) OVERRIDE; // Load/store register dual instructions using registers `rd` and `rd` + 1. void ldrd(Register rd, const Address& ad, Condition cond = AL) OVERRIDE; void strd(Register rd, const Address& ad, Condition cond = AL) OVERRIDE; // Load/store register dual instructions using registers `rd` and `rd2`. // Note that contrary to the ARM A1 encoding, the Thumb-2 T1 encoding // does not require `rd` to be even, nor `rd2' to be equal to `rd` + 1. void ldrd(Register rd, Register rd2, const Address& ad, Condition cond); void strd(Register rd, Register rd2, const Address& ad, Condition cond); void ldm(BlockAddressMode am, Register base, RegList regs, Condition cond = AL) OVERRIDE; void stm(BlockAddressMode am, Register base, RegList regs, Condition cond = AL) OVERRIDE; void ldrex(Register rd, Register rn, Condition cond = AL) OVERRIDE; void strex(Register rd, Register rt, Register rn, Condition cond = AL) OVERRIDE; void ldrex(Register rd, Register rn, uint16_t imm, Condition cond = AL); void strex(Register rd, Register rt, Register rn, uint16_t imm, Condition cond = AL); void ldrexd(Register rt, Register rt2, Register rn, Condition cond = AL) OVERRIDE; void strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond = AL) OVERRIDE; // Miscellaneous instructions. void clrex(Condition cond = AL) OVERRIDE; void nop(Condition cond = AL) OVERRIDE; void bkpt(uint16_t imm16) OVERRIDE; void svc(uint32_t imm24) OVERRIDE; // If-then void it(Condition firstcond, ItState i1 = kItOmitted, ItState i2 = kItOmitted, ItState i3 = kItOmitted) OVERRIDE; void cbz(Register rn, Label* target) OVERRIDE; void cbnz(Register rn, Label* target) OVERRIDE; // Floating point instructions (VFPv3-D16 and VFPv3-D32 profiles). void vmovsr(SRegister sn, Register rt, Condition cond = AL) OVERRIDE; void vmovrs(Register rt, SRegister sn, Condition cond = AL) OVERRIDE; void vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond = AL) OVERRIDE; void vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond = AL) OVERRIDE; void vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond = AL) OVERRIDE; void vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond = AL) OVERRIDE; void vmovs(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE; void vmovd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE; // Returns false if the immediate cannot be encoded. bool vmovs(SRegister sd, float s_imm, Condition cond = AL) OVERRIDE; bool vmovd(DRegister dd, double d_imm, Condition cond = AL) OVERRIDE; void vldrs(SRegister sd, const Address& ad, Condition cond = AL) OVERRIDE; void vstrs(SRegister sd, const Address& ad, Condition cond = AL) OVERRIDE; void vldrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE; void vstrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE; void vadds(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE; void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE; void vsubs(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE; void vsubd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE; void vmuls(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE; void vmuld(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE; void vmlas(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE; void vmlad(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE; void vmlss(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE; void vmlsd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE; void vdivs(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE; void vdivd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE; void vabss(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE; void vabsd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE; void vnegs(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE; void vnegd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE; void vsqrts(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE; void vsqrtd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE; void vcvtsd(SRegister sd, DRegister dm, Condition cond = AL) OVERRIDE; void vcvtds(DRegister dd, SRegister sm, Condition cond = AL) OVERRIDE; void vcvtis(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE; void vcvtid(SRegister sd, DRegister dm, Condition cond = AL) OVERRIDE; void vcvtsi(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE; void vcvtdi(DRegister dd, SRegister sm, Condition cond = AL) OVERRIDE; void vcvtus(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE; void vcvtud(SRegister sd, DRegister dm, Condition cond = AL) OVERRIDE; void vcvtsu(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE; void vcvtdu(DRegister dd, SRegister sm, Condition cond = AL) OVERRIDE; void vcmps(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE; void vcmpd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE; void vcmpsz(SRegister sd, Condition cond = AL) OVERRIDE; void vcmpdz(DRegister dd, Condition cond = AL) OVERRIDE; void vmstat(Condition cond = AL) OVERRIDE; // VMRS APSR_nzcv, FPSCR void vcntd(DRegister dd, DRegister dm) OVERRIDE; void vpaddld(DRegister dd, DRegister dm, int32_t size, bool is_unsigned) OVERRIDE; void vpushs(SRegister reg, int nregs, Condition cond = AL) OVERRIDE; void vpushd(DRegister reg, int nregs, Condition cond = AL) OVERRIDE; void vpops(SRegister reg, int nregs, Condition cond = AL) OVERRIDE; void vpopd(DRegister reg, int nregs, Condition cond = AL) OVERRIDE; void vldmiad(Register base_reg, DRegister reg, int nregs, Condition cond = AL) OVERRIDE; void vstmiad(Register base_reg, DRegister reg, int nregs, Condition cond = AL) OVERRIDE; // Branch instructions. void b(Label* label, Condition cond = AL); void bl(Label* label, Condition cond = AL); void blx(Label* label); void blx(Register rm, Condition cond = AL) OVERRIDE; void bx(Register rm, Condition cond = AL) OVERRIDE; // ADR instruction loading register for branching to the label, including the Thumb mode bit. void AdrCode(Register rt, Label* label) OVERRIDE; virtual void Lsl(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void Lsr(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void Asr(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void Ror(Register rd, Register rm, uint32_t shift_imm, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void Rrx(Register rd, Register rm, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void Lsl(Register rd, Register rm, Register rn, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void Lsr(Register rd, Register rm, Register rn, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void Asr(Register rd, Register rm, Register rn, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; virtual void Ror(Register rd, Register rm, Register rn, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; void Push(Register rd, Condition cond = AL) OVERRIDE; void Pop(Register rd, Condition cond = AL) OVERRIDE; void PushList(RegList regs, Condition cond = AL) OVERRIDE; void PopList(RegList regs, Condition cond = AL) OVERRIDE; void StoreList(RegList regs, size_t stack_offset) OVERRIDE; void LoadList(RegList regs, size_t stack_offset) OVERRIDE; void Mov(Register rd, Register rm, Condition cond = AL) OVERRIDE; void CompareAndBranchIfZero(Register r, Label* label) OVERRIDE; void CompareAndBranchIfNonZero(Register r, Label* label) OVERRIDE; // Memory barriers. void dmb(DmbOptions flavor) OVERRIDE; // Get the final position of a label after local fixup based on the old position // recorded before FinalizeCode(). uint32_t GetAdjustedPosition(uint32_t old_position) OVERRIDE; using ArmAssembler::NewLiteral; // Make the helper template visible. Literal* NewLiteral(size_t size, const uint8_t* data) OVERRIDE; void LoadLiteral(Register rt, Literal* literal) OVERRIDE; void LoadLiteral(Register rt, Register rt2, Literal* literal) OVERRIDE; void LoadLiteral(SRegister sd, Literal* literal) OVERRIDE; void LoadLiteral(DRegister dd, Literal* literal) OVERRIDE; // Add signed constant value to rd. May clobber IP. void AddConstant(Register rd, Register rn, int32_t value, Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE; void CmpConstant(Register rn, int32_t value, Condition cond = AL) OVERRIDE; // Load and Store. May clobber IP. void LoadImmediate(Register rd, int32_t value, Condition cond = AL) OVERRIDE; void LoadDImmediate(DRegister dd, double value, Condition cond = AL) OVERRIDE; void MarkExceptionHandler(Label* label) OVERRIDE; void LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset, Condition cond = AL) OVERRIDE; void StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset, Condition cond = AL) OVERRIDE; void LoadSFromOffset(SRegister reg, Register base, int32_t offset, Condition cond = AL) OVERRIDE; void StoreSToOffset(SRegister reg, Register base, int32_t offset, Condition cond = AL) OVERRIDE; void LoadDFromOffset(DRegister reg, Register base, int32_t offset, Condition cond = AL) OVERRIDE; void StoreDToOffset(DRegister reg, Register base, int32_t offset, Condition cond = AL) OVERRIDE; bool ShifterOperandCanHold(Register rd, Register rn, Opcode opcode, uint32_t immediate, SetCc set_cc, ShifterOperand* shifter_op) OVERRIDE; using ArmAssembler::ShifterOperandCanHold; // Don't hide the non-virtual override. bool ShifterOperandCanAlwaysHold(uint32_t immediate) OVERRIDE; static bool IsInstructionForExceptionHandling(uintptr_t pc); // Emit data (e.g. encoded instruction or immediate) to the. // instruction stream. void Emit32(int32_t value); // Emit a 32 bit instruction in thumb format. void Emit16(int16_t value); // Emit a 16 bit instruction in little endian format. void Bind(Label* label) OVERRIDE; // Force the assembler to generate 32 bit instructions. void Force32Bit() { force_32bit_ = true; } void Allow16Bit() { force_32bit_ = false; } // Emit an ADR (or a sequence of instructions) to load the jump table address into base_reg. This // will generate a fixup. JumpTable* CreateJumpTable(std::vector&& labels, Register base_reg) OVERRIDE; // Emit an ADD PC, X to dispatch a jump-table jump. This will generate a fixup. void EmitJumpTableDispatch(JumpTable* jump_table, Register displacement_reg) OVERRIDE; private: typedef uint16_t FixupId; // Fixup: branches and literal pool references. // // The thumb2 architecture allows branches to be either 16 or 32 bit instructions. This // depends on both the type of branch and the offset to which it is branching. The 16-bit // cbz and cbnz instructions may also need to be replaced with a separate 16-bit compare // instruction and a 16- or 32-bit branch instruction. Load from a literal pool can also be // 16-bit or 32-bit instruction and, if the method is large, we may need to use a sequence // of instructions to make up for the limited range of load literal instructions (up to // 4KiB for the 32-bit variant). When generating code for these insns we don't know the // size before hand, so we assume it is the smallest available size and determine the final // code offsets and sizes and emit code in FinalizeCode(). // // To handle this, we keep a record of every branch and literal pool load in the program. // The actual instruction encoding for these is delayed until we know the final size of // every instruction. When we bind a label to a branch we don't know the final location yet // as some preceding instructions may need to be expanded, so we record a non-final offset. // In FinalizeCode(), we expand the sizes of branches and literal loads that are out of // range. With each expansion, we need to update dependent Fixups, i.e. insntructios with // target on the other side of the expanded insn, as their offsets change and this may // trigger further expansion. // // All Fixups have a 'fixup id' which is a 16 bit unsigned number used to identify the // Fixup. For each unresolved label we keep a singly-linked list of all Fixups pointing // to it, using the fixup ids as links. The first link is stored in the label's position // (the label is linked but not bound), the following links are stored in the code buffer, // in the placeholder where we will eventually emit the actual code. class Fixup { public: // Branch type. enum Type : uint8_t { kConditional, // B. kUnconditional, // B. kUnconditionalLink, // BL. kUnconditionalLinkX, // BLX. kCompareAndBranchXZero, // cbz/cbnz. kLoadCodeAddr, // Get address of a code label, used for Baker read barriers. kLoadLiteralNarrow, // Load narrrow integer literal. kLoadLiteralWide, // Load wide integer literal. kLoadLiteralAddr, // Load address of literal (used for jump table). kLoadFPLiteralSingle, // Load FP literal single. kLoadFPLiteralDouble, // Load FP literal double. }; // Calculated size of branch instruction based on type and offset. enum Size : uint8_t { // Branch variants. kBranch16Bit, kBranch32Bit, // NOTE: We don't support branches which would require multiple instructions, i.e. // conditinoal branches beyond +-1MiB and unconditional branches beyond +-16MiB. // CBZ/CBNZ variants. kCbxz16Bit, // CBZ/CBNZ rX, label; X < 8; 7-bit positive offset. kCbxz32Bit, // CMP rX, #0 + Bcc label; X < 8; 16-bit Bcc; +-8-bit offset. kCbxz48Bit, // CMP rX, #0 + Bcc label; X < 8; 32-bit Bcc; up to +-1MiB offset. // ADR variants. kCodeAddr4KiB, // ADR rX,