From c4b188db0eb42d9639e5f66d0d063105024f8960 Mon Sep 17 00:00:00 2001 From: Artem Serov Date: Wed, 28 Sep 2022 16:06:15 +0100 Subject: Don't use predicated vectorization by default. This patch sets the traditional vectorization mode to be the default one; previously, if the target supported predicated vectorization (e.g. arm64 SVE), predicated vectorization was be tried for ALL loops. Motivation: this is a prerequisite for the further patches to enable mixed mode vectorization - when most of the loops are vectorized in traditional mode and some others - in predicated. A new env variable - ART_FORCE_TRY_PREDICATED_SIMD - is introduced to force-use the predicated mode; this could be set to true for testing purposes. Checker tests are adjusted accordingly - to also check the ART_FORCE_TRY_PREDICATED_SIMD variable. Test: test-art-target, test-art-host. Test: test-art-target with ART_FORCE_TRY_PREDICATED_SIMD=true. Original author: Artem Serov Test: ./art/test/testrunner/testrunner.py --host --optimizing --jit Test: ./art/test/testrunner/testrunner.py --target --optimizing --jit (with ART_FORCE_TRY_PREDICATED_SIMD=true and without) Test: 661-checker-simd-cf-loops. Test: target tests on arm64 with SVE Change-Id: I57852f3777da6f86d615429d1a3c703cb87fbac8 --- test/527-checker-array-access-simd/src/Main.java | 28 ++++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'test/527-checker-array-access-simd/src/Main.java') diff --git a/test/527-checker-array-access-simd/src/Main.java b/test/527-checker-array-access-simd/src/Main.java index a08b1f09b4..a26efaeefe 100644 --- a/test/527-checker-array-access-simd/src/Main.java +++ b/test/527-checker-array-access-simd/src/Main.java @@ -25,7 +25,7 @@ public class Main { /// CHECK-START-ARM64: void Main.checkIntCase(int[]) instruction_simplifier_arm64 (before) /// CHECK-DAG: <> ParameterValue /// CHECK-DAG: <> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <> VecReplicateScalar [<>,{{j\d+}}] // -------------- Loop @@ -51,7 +51,7 @@ public class Main { /// CHECK-START-ARM64: void Main.checkIntCase(int[]) instruction_simplifier_arm64 (after) /// CHECK-DAG: <> ParameterValue /// CHECK-DAG: <> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. /// CHECK-DAG: <> VecReplicateScalar [<>,{{j\d+}}] @@ -84,7 +84,7 @@ public class Main { /// CHECK-START-ARM64: void Main.checkIntCase(int[]) GVN$after_arch (after) /// CHECK-DAG: <> ParameterValue /// CHECK-DAG: <> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. /// CHECK-DAG: <> VecReplicateScalar [<>,{{j\d+}}] @@ -114,7 +114,7 @@ public class Main { /// CHECK-FI: /// CHECK-START-ARM64: void Main.checkIntCase(int[]) disassembly (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. /// CHECK-NOT: IntermediateAddressIndex @@ -134,7 +134,7 @@ public class Main { /// CHECK-START-ARM64: void Main.checkByteCase(byte[]) instruction_simplifier_arm64 (before) /// CHECK-DAG: <> ParameterValue /// CHECK-DAG: <> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <> VecReplicateScalar [<>,{{j\d+}}] // -------------- Loop @@ -161,7 +161,7 @@ public class Main { /// CHECK-DAG: <> ParameterValue /// CHECK-DAG: <> IntConstant 0 /// CHECK-DAG: <> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. /// CHECK-DAG: <> VecReplicateScalar [<>,{{j\d+}}] @@ -194,7 +194,7 @@ public class Main { /// CHECK-DAG: <> ParameterValue /// CHECK-DAG: <> IntConstant 0 /// CHECK-DAG: <> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. /// CHECK-DAG: <> VecReplicateScalar [<>,{{j\d+}}] @@ -223,7 +223,7 @@ public class Main { /// CHECK-FI: /// CHECK-START-ARM64: void Main.checkByteCase(byte[]) disassembly (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. /// CHECK-NOT: IntermediateAddressIndex @@ -247,7 +247,7 @@ public class Main { /// CHECK-START-ARM64: void Main.checkSingleAccess(int[]) instruction_simplifier_arm64 (before) /// CHECK-DAG: <> ParameterValue /// CHECK-DAG: <> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <> VecReplicateScalar [<>,{{j\d+}}] // -------------- Loop @@ -270,7 +270,7 @@ public class Main { /// CHECK-DAG: <> ParameterValue /// CHECK-DAG: <> IntConstant 0 /// CHECK-DAG: <> IntConstant 5 - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <> VecReplicateScalar [<>,{{j\d+}}] // -------------- Loop @@ -301,7 +301,7 @@ public class Main { /// CHECK-DAG: <> ParameterValue /// CHECK-DAG: <> ParameterValue // -------------- Loop - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // /// CHECK-DAG: <> VecPredWhile /// CHECK-DAG: <> Phi @@ -323,7 +323,7 @@ public class Main { /// CHECK-START-ARM64: void Main.checkInt2Float(int[], float[]) instruction_simplifier_arm64 (after) /// CHECK-DAG: <> ParameterValue /// CHECK-DAG: <> ParameterValue - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. // -------------- Loop @@ -354,7 +354,7 @@ public class Main { /// CHECK-START-ARM64: void Main.checkInt2Float(int[], float[]) GVN$after_arch (after) /// CHECK-DAG: <> ParameterValue /// CHECK-DAG: <> ParameterValue - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. // -------------- Loop @@ -383,7 +383,7 @@ public class Main { /// CHECK-FI: /// CHECK-START-ARM64: void Main.checkInt2Float(int[], float[]) disassembly (after) - /// CHECK-IF: hasIsaFeature("sve") + /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true' // // IntermediateAddressIndex is not supported for SVE. /// CHECK-NOT: IntermediateAddressIndex -- cgit v1.2.3-59-g8ed1b