From e196567b50a084b163937ea9605b51ee1e48adeb Mon Sep 17 00:00:00 2001 From: buzbee Date: Sun, 11 Mar 2012 18:39:19 -0700 Subject: SSA rework and support compiler temps in the frame Add ability for the compiler to allocate new frame temporaries that play nicely with the register allocation mechanism. To do this we assign negative virtual register numbers and give them SSA names. As part of this change, I did a general cleanup of the ssa naming. An ssa name (or SReg) is in index into an array of (virtual reg, subscript) pairs. Previously, 16 bits were allocated for the reg and the subscript. This CL expands the virtual reg and subscript to 32 bits each. Method* is now treated as a RegLocation, and will be subject to temp register tracking and reuse. This CL does not yet include support for promotion of Method* - that will show up in the next one. Also included is the beginning of a basic block optimization pass (not yet in a runable state, so conditionally compiled out). (cherry picked from commit f689ffec8827f1dd6b31084f8a6bb240338c7acf) Change-Id: Ibbdeb97fe05d0e33c1f4a9a6ccbdef1cac7646fc --- src/compiler/codegen/arm/ArchFactory.cc | 16 +++++++++++++++- src/compiler/codegen/arm/ArmRallocUtil.cc | 8 ++++---- src/compiler/codegen/arm/Thumb2/Ralloc.cc | 4 ++++ 3 files changed, 23 insertions(+), 5 deletions(-) (limited to 'src/compiler/codegen/arm') diff --git a/src/compiler/codegen/arm/ArchFactory.cc b/src/compiler/codegen/arm/ArchFactory.cc index 8a23d5c2e1..da5de521f3 100644 --- a/src/compiler/codegen/arm/ArchFactory.cc +++ b/src/compiler/codegen/arm/ArchFactory.cc @@ -106,7 +106,21 @@ void genEntrySequence(CompilationUnit* cUnit, BasicBlock* bb) opRegImm(cUnit, kOpSub, rSP, cUnit->frameSize - (spillCount * 4)); } - storeBaseDisp(cUnit, rSP, 0, r0, kWord); + + /* + * Dummy up a RegLocation for the incoming Method* + * It will attempt to keep r0 live (or copy it to home location + * if promoted). + */ + RegLocation rlSrc = cUnit->regLocation[cUnit->methodSReg]; + RegLocation rlMethod = cUnit->regLocation[cUnit->methodSReg]; + rlSrc.location = kLocPhysReg; + rlSrc.lowReg = r0; + rlSrc.home = false; + oatMarkLive(cUnit, rlSrc.lowReg, rlSrc.sRegLow); + storeValue(cUnit, rlMethod, rlSrc); + + /* Flush the rest of the ins */ flushIns(cUnit); if (cUnit->genDebugger) { diff --git a/src/compiler/codegen/arm/ArmRallocUtil.cc b/src/compiler/codegen/arm/ArmRallocUtil.cc index 3335f5997e..e7627f2367 100644 --- a/src/compiler/codegen/arm/ArmRallocUtil.cc +++ b/src/compiler/codegen/arm/ArmRallocUtil.cc @@ -76,10 +76,10 @@ void oatFlushRegWide(CompilationUnit* cUnit, int reg1, int reg2) info1->dirty = false; info2->dirty = false; - if (oatS2VReg(cUnit, info2->sReg) < - oatS2VReg(cUnit, info1->sReg)) + if (SRegToVReg(cUnit, info2->sReg) < + SRegToVReg(cUnit, info1->sReg)) info1 = info2; - int vReg = oatS2VReg(cUnit, info1->sReg); + int vReg = SRegToVReg(cUnit, info1->sReg); oatFlushRegWideImpl(cUnit, rSP, oatVRegOffset(cUnit, vReg), info1->reg, info1->partner); @@ -91,7 +91,7 @@ void oatFlushReg(CompilationUnit* cUnit, int reg) RegisterInfo* info = oatGetRegInfo(cUnit, reg); if (info->live && info->dirty) { info->dirty = false; - int vReg = oatS2VReg(cUnit, info->sReg); + int vReg = SRegToVReg(cUnit, info->sReg); oatFlushRegImpl(cUnit, rSP, oatVRegOffset(cUnit, vReg), reg, kWord); diff --git a/src/compiler/codegen/arm/Thumb2/Ralloc.cc b/src/compiler/codegen/arm/Thumb2/Ralloc.cc index c0f2c771ca..7858318001 100644 --- a/src/compiler/codegen/arm/Thumb2/Ralloc.cc +++ b/src/compiler/codegen/arm/Thumb2/Ralloc.cc @@ -88,6 +88,10 @@ void oatInitializeRegAlloc(CompilationUnit* cUnit) for (int i = 0; i < numFPTemps; i++) { oatMarkTemp(cUnit, fpTemps[i]); } + + // Start allocation at r2 in an attempt to avoid clobbering return values + pool->nextCoreReg = r2; + // Construct the alias map. cUnit->phiAliasMap = (int*)oatNew(cUnit, cUnit->numSSARegs * sizeof(cUnit->phiAliasMap[0]), false, -- cgit v1.2.3-59-g8ed1b