From ad8f15e0b13383b2eaa2486b230debeae7a55661 Mon Sep 17 00:00:00 2001 From: buzbee Date: Mon, 18 Jun 2012 14:49:45 -0700 Subject: Milestone: close Quick side channel communication This CL elminates side-channel communication between the Quick Compiler's Dex->MIR->LLVM-IR and LLVM-IR->LIR lowering stages by clearing key data structures between the two stages. The purpose if to flush out any hidden information transfer, and thus ensure that the GreenlandIR representation of the program is sufficient. Note that as of this change, we've lost all register promotion info so the Quick compiler will generate non-promoted code. A near-future CL will restore that info from the MethodInfo intrinsic. Change-Id: I797845f1fc029bc03aac3ec20f8cd81f917817ca --- src/compiler/codegen/RallocUtil.cc | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'src/compiler/codegen/RallocUtil.cc') diff --git a/src/compiler/codegen/RallocUtil.cc b/src/compiler/codegen/RallocUtil.cc index e2f2cd683b..074fd26ca0 100644 --- a/src/compiler/codegen/RallocUtil.cc +++ b/src/compiler/codegen/RallocUtil.cc @@ -29,17 +29,6 @@ namespace art { -#define SREG(c, s) ((c)->regLocation[(s)].sRegLow) -/* - * Get the "real" sreg number associated with an sReg slot. In general, - * sReg values passed through codegen are the SSA names created by - * dataflow analysis and refer to slot numbers in the cUnit->regLocation - * array. However, renaming is accomplished by simply replacing RegLocation - * entries in the cUnit->reglocation[] array. Therefore, when location - * records for operands are first created, we need to ask the locRecord - * identified by the dataflow pass what it's new name is. - */ - /* * Free all allocated temps in the temp pools. Note that this does * not affect the "liveness" of a temp register, which will stay -- cgit v1.2.3-59-g8ed1b