From e296248a124ed8287b38a9225463696c18d84cd6 Mon Sep 17 00:00:00 2001
From: jeffhao <jeffhao@google.com>
Date: Thu, 28 Jun 2012 11:29:57 -0700
Subject: Fixes for x86 compiler optimizations.

x86 works with all but a few optimizations turned on, and the broken
ones are still disabled for now. This change includes:

- Flagging of opcodes to incidate register use and def. Also, made
  flagging more complete for loads/stores and set/use ccodes.

- Fixes to load store elimination, though it still doesn't work yet.

- Prevent double values that are loaded or stored from losing their
  FP_DOUBLE flag. Later optimizations use this sizing.

- Renumbering of DOUBLE registers so they alias with FP regs when
  masked.

- Add support in the disassembler to recognize shifts.

Change-Id: I758cdce418409fdd84206ce295005d5c9ab635f8
---
 src/compiler/codegen/CodegenUtil.cc | 35 +++++++++++++++++++++++++++++++++--
 1 file changed, 33 insertions(+), 2 deletions(-)

(limited to 'src/compiler/codegen/CodegenUtil.cc')

diff --git a/src/compiler/codegen/CodegenUtil.cc b/src/compiler/codegen/CodegenUtil.cc
index c189eb2795..428b4432f2 100644
--- a/src/compiler/codegen/CodegenUtil.cc
+++ b/src/compiler/codegen/CodegenUtil.cc
@@ -76,10 +76,17 @@ inline u8 getRegMaskCommon(int reg)
   int shift;
   int regId = reg & 0x1f;
 
+#if defined(TARGET_X86)
+  /*
+   * Double registers in x86 are just a single FP register
+   */
+  seed = 1;
+#else
   /*
    * Each double register is equal to a pair of single-precision FP registers
    */
   seed = DOUBLEREG(reg) ? 3 : 1;
+#endif
   /* FP register starts at bit position 16 */
   shift = FPREG(reg) ? kFPReg0 : 0;
   /* Expand the double register id into single offset */
@@ -140,6 +147,16 @@ void setupResourceMasks(LIR* lir)
     setupRegMask(&lir->defMask, lir->operands[1]);
   }
 
+#if defined(TARGET_X86)
+  if (flags & REG_DEFA) {
+    setupRegMask(&lir->defMask, rAX);
+  }
+
+  if (flags & REG_DEFD) {
+    setupRegMask(&lir->defMask, rDX);
+  }
+#endif
+
   if (flags & REG_DEF_SP) {
     lir->defMask |= ENCODE_REG_SP;
   }
@@ -150,6 +167,7 @@ void setupResourceMasks(LIR* lir)
   }
 #endif
 
+#if defined(TARGET_ARM)
   if (flags & REG_DEF_LIST0) {
     lir->defMask |= ENCODE_REG_LIST(lir->operands[0]);
   }
@@ -158,7 +176,6 @@ void setupResourceMasks(LIR* lir)
     lir->defMask |= ENCODE_REG_LIST(lir->operands[1]);
   }
 
-#if defined(TARGET_ARM)
   if (flags & REG_DEF_FPCS_LIST0) {
     lir->defMask |= ENCODE_REG_FPCS_LIST(lir->operands[0]);
   }
@@ -191,6 +208,20 @@ void setupResourceMasks(LIR* lir)
     }
   }
 
+#if defined(TARGET_X86)
+  if (flags & REG_USEA) {
+    setupRegMask(&lir->useMask, rAX);
+  }
+
+  if (flags & REG_USEC) {
+    setupRegMask(&lir->useMask, rCX);
+  }
+
+  if (flags & REG_USED) {
+    setupRegMask(&lir->useMask, rDX);
+  }
+#endif
+
 #if defined(TARGET_ARM)
   if (flags & REG_USE_PC) {
     lir->useMask |= ENCODE_REG_PC;
@@ -201,6 +232,7 @@ void setupResourceMasks(LIR* lir)
     lir->useMask |= ENCODE_REG_SP;
   }
 
+#if defined(TARGET_ARM)
   if (flags & REG_USE_LIST0) {
     lir->useMask |= ENCODE_REG_LIST(lir->operands[0]);
   }
@@ -209,7 +241,6 @@ void setupResourceMasks(LIR* lir)
     lir->useMask |= ENCODE_REG_LIST(lir->operands[1]);
   }
 
-#if defined(TARGET_ARM)
   if (flags & REG_USE_FPCS_LIST0) {
     lir->useMask |= ENCODE_REG_FPCS_LIST(lir->operands[0]);
   }
-- 
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