From 67d3fd77d1572e46f537dea2fd4ded3ecfd7c202 Mon Sep 17 00:00:00 2001 From: Aart Bik Date: Fri, 31 Mar 2017 15:11:53 -0700 Subject: SIMD pavgb,w for x86/x86_64 Rationale: Break-out CL of ART Vectorizer. Enables fast halving add with rounding Bug: 34083438 Test: assembler_x86[_64]_test Change-Id: I09173376b803d671a6b05a33e630f45f778cea52 --- disassembler/disassembler_x86.cc | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'disassembler/disassembler_x86.cc') diff --git a/disassembler/disassembler_x86.cc b/disassembler/disassembler_x86.cc index 77ed3c6a22..f5c3ad20cc 100644 --- a/disassembler/disassembler_x86.cc +++ b/disassembler/disassembler_x86.cc @@ -1101,6 +1101,22 @@ DISASSEMBLER_ENTRY(cmp, opcode1 = opcode_tmp.c_str(); } break; + case 0xE0: + case 0xE3: + if (prefix[2] == 0x66) { + src_reg_file = dst_reg_file = SSE; + prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode + } else { + src_reg_file = dst_reg_file = MMX; + } + switch (*instr) { + case 0xE0: opcode1 = "pavgb"; break; + case 0xE3: opcode1 = "pavgw"; break; + } + prefix[2] = 0; + has_modrm = true; + load = true; + break; case 0xEB: if (prefix[2] == 0x66) { src_reg_file = dst_reg_file = SSE; -- cgit v1.2.3-59-g8ed1b