From 8feddbc07bd1e05ed7aa5cf5fc66f7b2c3c24c31 Mon Sep 17 00:00:00 2001 From: Vladimir Marko Date: Thu, 3 Sep 2020 09:59:45 +0100 Subject: Improve disasembly of BL to thread entrypoint trampoline. Test: Manual, search for "\bbl\b" in `m dump-oat` output and oatdump of an individual oat file for arm and arm64. Change-Id: Idb6d8d1a21b2aa8c77e5b72f24faf7a4e655294c --- disassembler/disassembler_arm.cc | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'disassembler/disassembler_arm.cc') diff --git a/disassembler/disassembler_arm.cc b/disassembler/disassembler_arm.cc index 94ea0064e6..c2156ca5e1 100644 --- a/disassembler/disassembler_arm.cc +++ b/disassembler/disassembler_arm.cc @@ -68,6 +68,22 @@ class DisassemblerArm::CustomDisassembler final : public PrintDisassembler { PrintLiteral(type, offset); return *this; } + case kCodeLocation: + DisassemblerStream::operator<<(label); + // Improve the disassembly of branch to thunk jumping to pointer from thread entrypoint. + if (disasm_->GetIsT32() && GetCurrentInstructionType() == vixl::aarch32::kBl) { + const uintptr_t begin = reinterpret_cast(options_->base_address_); + const uintptr_t end = reinterpret_cast(options_->end_address_); + uintptr_t address = label.GetLocation() + (options_->absolute_addresses_ ? 0u : begin); + if ((address >= begin && address < end && end - address >= 4u) && + reinterpret_cast(address)[0] == 0xf8d9 && // LDR Rt, [tr, #imm12] + (reinterpret_cast(address)[1] >> 12) == 0xf) { // Rt == PC + uint32_t imm12 = reinterpret_cast(address)[1] & 0xfffu; + os() << " ; "; + options_->thread_offset_name_function_(os(), imm12); + } + } + return *this; default: return DisassemblerStream::operator<<(label); } -- cgit v1.2.3-59-g8ed1b