From dbce0d738e9d7956d2bd73e932a0fdd28f2229b4 Mon Sep 17 00:00:00 2001 From: Chris Larsen Date: Thu, 17 Sep 2015 13:34:00 -0700 Subject: MIPS64r6 Assembler Tests Assembler tests for: - SQRT.fmt - ABS.fmt - ROUND.L.fmt - ROUND.W.fmt - CEIL.L.fmt - CEIL.W.fmt - FLOOR.L.fmt - FLOOR.W.fmt - SEL.fmt - RINT.fmt - CLASS.fmt - MIN.fmt - MAX.fmt - cvt.d.l - BITSWAP - DBITSWAP - DSBH - DSHD - WSBH - ROTR - SELEQZ - SELNEZ - CLZ - CLO - DCLZ - DCLO - SC - SCD - LL - LLD These are the assembler instructions which were added to support intrinsic functions on MIPS64. Tests for additional assembler instructions will follow. Support added to the testing infrastructure for: - Assembler instructions which use three registers; previously instructions were limited to one, or two, registers. - Immediate values which have their sizes specified by the number of bits required to store them rather than the number of bytes, in both signed and unsigned versions. Change-Id: I38c07dcbf2539825b25bed13aac05a26fa594b0b --- compiler/utils/arm/assembler_arm32_test.cc | 2 +- compiler/utils/assembler_test.h | 202 ++++++++++++- compiler/utils/mips64/assembler_mips64_test.cc | 380 +++++++++++++++++++++++++ 3 files changed, 576 insertions(+), 8 deletions(-) create mode 100644 compiler/utils/mips64/assembler_mips64_test.cc (limited to 'compiler') diff --git a/compiler/utils/arm/assembler_arm32_test.cc b/compiler/utils/arm/assembler_arm32_test.cc index 2a0912e02d..43805966a9 100644 --- a/compiler/utils/arm/assembler_arm32_test.cc +++ b/compiler/utils/arm/assembler_arm32_test.cc @@ -287,7 +287,7 @@ class AssemblerArm32Test : public AssemblerArmTest(f, + GetRegisters(), + GetRegisters(), + GetRegisters(), + &AssemblerTest::GetRegName, + &AssemblerTest::GetRegName, + &AssemblerTest::GetRegName, + fmt); + } + std::string Repeatrb(void (Ass::*f)(Reg, Reg), std::string fmt) { return RepeatTemplatedRegisters(f, GetRegisters(), @@ -118,6 +129,66 @@ class AssemblerTest : public testing::Test { return RepeatRegisterImm(f, imm_bytes, fmt); } + template + std::string RepeatRegRegImmBits(void (Ass::*f)(Reg1Type, Reg2Type, ImmType), + int imm_bits, + std::string fmt) { + const std::vector reg1_registers = GetRegisters(); + const std::vector reg2_registers = GetRegisters(); + std::string str; + std::vector imms = CreateImmediateValuesBits(abs(imm_bits), imm_bits > 0); + + for (auto reg1 : reg1_registers) { + for (auto reg2 : reg2_registers) { + for (int64_t imm : imms) { + ImmType new_imm = CreateImmediate(imm); + (assembler_.get()->*f)(*reg1, *reg2, new_imm); + std::string base = fmt; + + std::string reg1_string = GetRegName(*reg1); + size_t reg1_index; + while ((reg1_index = base.find(REG1_TOKEN)) != std::string::npos) { + base.replace(reg1_index, ConstexprStrLen(REG1_TOKEN), reg1_string); + } + + std::string reg2_string = GetRegName(*reg2); + size_t reg2_index; + while ((reg2_index = base.find(REG2_TOKEN)) != std::string::npos) { + base.replace(reg2_index, ConstexprStrLen(REG2_TOKEN), reg2_string); + } + + size_t imm_index = base.find(IMM_TOKEN); + if (imm_index != std::string::npos) { + std::ostringstream sreg; + sreg << imm; + std::string imm_string = sreg.str(); + base.replace(imm_index, ConstexprStrLen(IMM_TOKEN), imm_string); + } + + if (str.size() > 0) { + str += "\n"; + } + str += base; + } + } + } + // Add a newline at the end. + str += "\n"; + return str; + } + + template + std::string RepeatRRIb(void (Ass::*f)(Reg1Type, Reg2Type, ImmType), + int imm_bits, + std::string fmt) { + return RepeatRegRegImmBits(f, imm_bits, fmt); + } + std::string RepeatFF(void (Ass::*f)(FPReg, FPReg), std::string fmt) { return RepeatTemplatedRegisters(f, GetFPRegisters(), @@ -127,14 +198,27 @@ class AssemblerTest : public testing::Test { fmt); } - std::string RepeatFFI(void (Ass::*f)(FPReg, FPReg, const Imm&), size_t imm_bytes, std::string fmt) { + std::string RepeatFFF(void (Ass::*f)(FPReg, FPReg, FPReg), std::string fmt) { + return RepeatTemplatedRegisters(f, + GetFPRegisters(), + GetFPRegisters(), + GetFPRegisters(), + &AssemblerTest::GetFPRegName, + &AssemblerTest::GetFPRegName, + &AssemblerTest::GetFPRegName, + fmt); + } + + std::string RepeatFFI(void (Ass::*f)(FPReg, FPReg, const Imm&), + size_t imm_bytes, + std::string fmt) { return RepeatTemplatedRegistersImm(f, - GetFPRegisters(), - GetFPRegisters(), - &AssemblerTest::GetFPRegName, - &AssemblerTest::GetFPRegName, - imm_bytes, - fmt); + GetFPRegisters(), + GetFPRegisters(), + &AssemblerTest::GetFPRegName, + &AssemblerTest::GetFPRegName, + imm_bytes, + fmt); } std::string RepeatFR(void (Ass::*f)(FPReg, Reg), std::string fmt) { @@ -339,6 +423,63 @@ class AssemblerTest : public testing::Test { return res; } + const int kMaxBitsExhaustiveTest = 8; + + // Create a couple of immediate values up to the number of bits given. + virtual std::vector CreateImmediateValuesBits(const int imm_bits, bool as_uint = false) { + CHECK_GT(imm_bits, 0); + CHECK_LE(imm_bits, 64); + std::vector res; + + if (imm_bits <= kMaxBitsExhaustiveTest) { + if (as_uint) { + for (uint64_t i = MinInt(imm_bits); i <= MaxInt(imm_bits); i++) { + res.push_back(static_cast(i)); + } + } else { + for (int64_t i = MinInt(imm_bits); i <= MaxInt(imm_bits); i++) { + res.push_back(i); + } + } + } else { + if (as_uint) { + for (uint64_t i = MinInt(kMaxBitsExhaustiveTest); + i <= MaxInt(kMaxBitsExhaustiveTest); + i++) { + res.push_back(static_cast(i)); + } + for (int i = 0; i <= imm_bits; i++) { + uint64_t j = (MaxInt(kMaxBitsExhaustiveTest) + 1) + + ((MaxInt(imm_bits) - + (MaxInt(kMaxBitsExhaustiveTest) + 1)) + * i / imm_bits); + res.push_back(static_cast(j)); + } + } else { + for (int i = 0; i <= imm_bits; i++) { + int64_t j = MinInt(imm_bits) + + ((((MinInt(kMaxBitsExhaustiveTest) - 1) - + MinInt(imm_bits)) + * i) / imm_bits); + res.push_back(static_cast(j)); + } + for (int64_t i = MinInt(kMaxBitsExhaustiveTest); + i <= MaxInt(kMaxBitsExhaustiveTest); + i++) { + res.push_back(static_cast(i)); + } + for (int i = 0; i <= imm_bits; i++) { + int64_t j = (MaxInt(kMaxBitsExhaustiveTest) + 1) + + ((MaxInt(imm_bits) - (MaxInt(kMaxBitsExhaustiveTest) + 1)) + * i / imm_bits); + res.push_back(static_cast(j)); + } + } + } + + return res; + } + // Create an immediate from the specific value. virtual Imm CreateImmediate(int64_t imm_value) = 0; @@ -406,6 +547,52 @@ class AssemblerTest : public testing::Test { return str; } + template + std::string RepeatTemplatedRegisters(void (Ass::*f)(Reg1, Reg2, Reg3), + const std::vector reg1_registers, + const std::vector reg2_registers, + const std::vector reg3_registers, + std::string (AssemblerTest::*GetName1)(const Reg1&), + std::string (AssemblerTest::*GetName2)(const Reg2&), + std::string (AssemblerTest::*GetName3)(const Reg3&), + std::string fmt) { + std::string str; + for (auto reg1 : reg1_registers) { + for (auto reg2 : reg2_registers) { + for (auto reg3 : reg3_registers) { + (assembler_.get()->*f)(*reg1, *reg2, *reg3); + std::string base = fmt; + + std::string reg1_string = (this->*GetName1)(*reg1); + size_t reg1_index; + while ((reg1_index = base.find(REG1_TOKEN)) != std::string::npos) { + base.replace(reg1_index, ConstexprStrLen(REG1_TOKEN), reg1_string); + } + + std::string reg2_string = (this->*GetName2)(*reg2); + size_t reg2_index; + while ((reg2_index = base.find(REG2_TOKEN)) != std::string::npos) { + base.replace(reg2_index, ConstexprStrLen(REG2_TOKEN), reg2_string); + } + + std::string reg3_string = (this->*GetName3)(*reg3); + size_t reg3_index; + while ((reg3_index = base.find(REG3_TOKEN)) != std::string::npos) { + base.replace(reg3_index, ConstexprStrLen(REG3_TOKEN), reg3_string); + } + + if (str.size() > 0) { + str += "\n"; + } + str += base; + } + } + } + // Add a newline at the end. + str += "\n"; + return str; + } + template std::string RepeatTemplatedRegistersImm(void (Ass::*f)(Reg1, Reg2, const Imm&), const std::vector reg1_registers, @@ -500,6 +687,7 @@ class AssemblerTest : public testing::Test { static constexpr const char* REG_TOKEN = "{reg}"; static constexpr const char* REG1_TOKEN = "{reg1}"; static constexpr const char* REG2_TOKEN = "{reg2}"; + static constexpr const char* REG3_TOKEN = "{reg3}"; static constexpr const char* IMM_TOKEN = "{imm}"; private: diff --git a/compiler/utils/mips64/assembler_mips64_test.cc b/compiler/utils/mips64/assembler_mips64_test.cc new file mode 100644 index 0000000000..2071aca546 --- /dev/null +++ b/compiler/utils/mips64/assembler_mips64_test.cc @@ -0,0 +1,380 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "assembler_mips64.h" + +#include +#include +#include + +#include "base/bit_utils.h" +#include "base/stl_util.h" +#include "utils/assembler_test.h" + +namespace art { + +struct MIPS64CpuRegisterCompare { + bool operator()(const mips64::GpuRegister& a, const mips64::GpuRegister& b) const { + return a < b; + } +}; + +class AssemblerMIPS64Test : public AssemblerTest { + public: + typedef AssemblerTest Base; + + protected: + // Get the typically used name for this architecture, e.g., aarch64, x86-64, ... + std::string GetArchitectureString() OVERRIDE { + return "mips64"; + } + + std::string GetAssemblerParameters() OVERRIDE { + return " --no-warn -march=mips64r6"; + } + + std::string GetDisassembleParameters() OVERRIDE { + return " -D -bbinary -mmips:isa64r6"; + } + + void SetUpHelpers() OVERRIDE { + if (registers_.size() == 0) { + registers_.push_back(new mips64::GpuRegister(mips64::ZERO)); + registers_.push_back(new mips64::GpuRegister(mips64::AT)); + registers_.push_back(new mips64::GpuRegister(mips64::V0)); + registers_.push_back(new mips64::GpuRegister(mips64::V1)); + registers_.push_back(new mips64::GpuRegister(mips64::A0)); + registers_.push_back(new mips64::GpuRegister(mips64::A1)); + registers_.push_back(new mips64::GpuRegister(mips64::A2)); + registers_.push_back(new mips64::GpuRegister(mips64::A3)); + registers_.push_back(new mips64::GpuRegister(mips64::A4)); + registers_.push_back(new mips64::GpuRegister(mips64::A5)); + registers_.push_back(new mips64::GpuRegister(mips64::A6)); + registers_.push_back(new mips64::GpuRegister(mips64::A7)); + registers_.push_back(new mips64::GpuRegister(mips64::T0)); + registers_.push_back(new mips64::GpuRegister(mips64::T1)); + registers_.push_back(new mips64::GpuRegister(mips64::T2)); + registers_.push_back(new mips64::GpuRegister(mips64::T3)); + registers_.push_back(new mips64::GpuRegister(mips64::S0)); + registers_.push_back(new mips64::GpuRegister(mips64::S1)); + registers_.push_back(new mips64::GpuRegister(mips64::S2)); + registers_.push_back(new mips64::GpuRegister(mips64::S3)); + registers_.push_back(new mips64::GpuRegister(mips64::S4)); + registers_.push_back(new mips64::GpuRegister(mips64::S5)); + registers_.push_back(new mips64::GpuRegister(mips64::S6)); + registers_.push_back(new mips64::GpuRegister(mips64::S7)); + registers_.push_back(new mips64::GpuRegister(mips64::T8)); + registers_.push_back(new mips64::GpuRegister(mips64::T9)); + registers_.push_back(new mips64::GpuRegister(mips64::K0)); + registers_.push_back(new mips64::GpuRegister(mips64::K1)); + registers_.push_back(new mips64::GpuRegister(mips64::GP)); + registers_.push_back(new mips64::GpuRegister(mips64::SP)); + registers_.push_back(new mips64::GpuRegister(mips64::S8)); + registers_.push_back(new mips64::GpuRegister(mips64::RA)); + + secondary_register_names_.emplace(mips64::GpuRegister(mips64::ZERO), "zero"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::AT), "at"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::V0), "v0"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::V1), "v1"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::A0), "a0"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::A1), "a1"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::A2), "a2"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::A3), "a3"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::A4), "a4"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::A5), "a5"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::A6), "a6"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::A7), "a7"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::T0), "t0"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::T1), "t1"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::T2), "t2"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::T3), "t3"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::S0), "s0"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::S1), "s1"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::S2), "s2"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::S3), "s3"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::S4), "s4"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::S5), "s5"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::S6), "s6"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::S7), "s7"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::T8), "t8"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::T9), "t9"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::K0), "k0"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::K1), "k1"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::GP), "gp"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::SP), "sp"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::S8), "s8"); + secondary_register_names_.emplace(mips64::GpuRegister(mips64::RA), "ra"); + + fp_registers_.push_back(new mips64::FpuRegister(mips64::F0)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F1)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F2)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F3)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F4)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F5)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F6)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F7)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F8)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F9)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F10)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F11)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F12)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F13)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F14)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F15)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F16)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F17)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F18)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F19)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F20)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F21)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F22)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F23)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F24)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F25)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F26)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F27)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F28)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F29)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F30)); + fp_registers_.push_back(new mips64::FpuRegister(mips64::F31)); + } + } + + void TearDown() OVERRIDE { + AssemblerTest::TearDown(); + STLDeleteElements(®isters_); + STLDeleteElements(&fp_registers_); + } + + std::vector GetRegisters() OVERRIDE { + return registers_; + } + + std::vector GetFPRegisters() OVERRIDE { + return fp_registers_; + } + + uint32_t CreateImmediate(int64_t imm_value) OVERRIDE { + return imm_value; + } + + std::string GetSecondaryRegisterName(const mips64::GpuRegister& reg) OVERRIDE { + CHECK(secondary_register_names_.find(reg) != secondary_register_names_.end()); + return secondary_register_names_[reg]; + } + + private: + std::vector registers_; + std::map secondary_register_names_; + + std::vector fp_registers_; +}; + + +TEST_F(AssemblerMIPS64Test, Toolchain) { + EXPECT_TRUE(CheckTools()); +} + + +/////////////////// +// FP Operations // +/////////////////// + +TEST_F(AssemblerMIPS64Test, SqrtS) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::SqrtS, "sqrt.s ${reg1}, ${reg2}"), "sqrt.s"); +} + +TEST_F(AssemblerMIPS64Test, SqrtD) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::SqrtD, "sqrt.d ${reg1}, ${reg2}"), "sqrt.d"); +} + +TEST_F(AssemblerMIPS64Test, AbsS) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::AbsS, "abs.s ${reg1}, ${reg2}"), "abs.s"); +} + +TEST_F(AssemblerMIPS64Test, AbsD) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::AbsD, "abs.d ${reg1}, ${reg2}"), "abs.d"); +} + +TEST_F(AssemblerMIPS64Test, RoundLS) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::RoundLS, "round.l.s ${reg1}, ${reg2}"), "round.l.s"); +} + +TEST_F(AssemblerMIPS64Test, RoundLD) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::RoundLD, "round.l.d ${reg1}, ${reg2}"), "round.l.d"); +} + +TEST_F(AssemblerMIPS64Test, RoundWS) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::RoundWS, "round.w.s ${reg1}, ${reg2}"), "round.w.s"); +} + +TEST_F(AssemblerMIPS64Test, RoundWD) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::RoundWD, "round.w.d ${reg1}, ${reg2}"), "round.w.d"); +} + +TEST_F(AssemblerMIPS64Test, CeilLS) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::CeilLS, "ceil.l.s ${reg1}, ${reg2}"), "ceil.l.s"); +} + +TEST_F(AssemblerMIPS64Test, CeilLD) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::CeilLD, "ceil.l.d ${reg1}, ${reg2}"), "ceil.l.d"); +} + +TEST_F(AssemblerMIPS64Test, CeilWS) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::CeilWS, "ceil.w.s ${reg1}, ${reg2}"), "ceil.w.s"); +} + +TEST_F(AssemblerMIPS64Test, CeilWD) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::CeilWD, "ceil.w.d ${reg1}, ${reg2}"), "ceil.w.d"); +} + +TEST_F(AssemblerMIPS64Test, FloorLS) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::FloorLS, "floor.l.s ${reg1}, ${reg2}"), "floor.l.s"); +} + +TEST_F(AssemblerMIPS64Test, FloorLD) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::FloorLD, "floor.l.d ${reg1}, ${reg2}"), "floor.l.d"); +} + +TEST_F(AssemblerMIPS64Test, FloorWS) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::FloorWS, "floor.w.s ${reg1}, ${reg2}"), "floor.w.s"); +} + +TEST_F(AssemblerMIPS64Test, FloorWD) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::FloorWD, "floor.w.d ${reg1}, ${reg2}"), "floor.w.d"); +} + +TEST_F(AssemblerMIPS64Test, SelS) { + DriverStr(RepeatFFF(&mips64::Mips64Assembler::SelS, "sel.s ${reg1}, ${reg2}, ${reg3}"), "sel.s"); +} + +TEST_F(AssemblerMIPS64Test, SelD) { + DriverStr(RepeatFFF(&mips64::Mips64Assembler::SelD, "sel.d ${reg1}, ${reg2}, ${reg3}"), "sel.d"); +} + +TEST_F(AssemblerMIPS64Test, RintS) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::RintS, "rint.s ${reg1}, ${reg2}"), "rint.s"); +} + +TEST_F(AssemblerMIPS64Test, RintD) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::RintD, "rint.d ${reg1}, ${reg2}"), "rint.d"); +} + +TEST_F(AssemblerMIPS64Test, ClassS) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::ClassS, "class.s ${reg1}, ${reg2}"), "class.s"); +} + +TEST_F(AssemblerMIPS64Test, ClassD) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::ClassD, "class.d ${reg1}, ${reg2}"), "class.d"); +} + +TEST_F(AssemblerMIPS64Test, MinS) { + DriverStr(RepeatFFF(&mips64::Mips64Assembler::MinS, "min.s ${reg1}, ${reg2}, ${reg3}"), "min.s"); +} + +TEST_F(AssemblerMIPS64Test, MinD) { + DriverStr(RepeatFFF(&mips64::Mips64Assembler::MinD, "min.d ${reg1}, ${reg2}, ${reg3}"), "min.d"); +} + +TEST_F(AssemblerMIPS64Test, MaxS) { + DriverStr(RepeatFFF(&mips64::Mips64Assembler::MaxS, "max.s ${reg1}, ${reg2}, ${reg3}"), "max.s"); +} + +TEST_F(AssemblerMIPS64Test, MaxD) { + DriverStr(RepeatFFF(&mips64::Mips64Assembler::MaxD, "max.d ${reg1}, ${reg2}, ${reg3}"), "max.d"); +} + +TEST_F(AssemblerMIPS64Test, CvtDL) { + DriverStr(RepeatFF(&mips64::Mips64Assembler::Cvtdl, "cvt.d.l ${reg1}, ${reg2}"), "cvt.d.l"); +} + +////////// +// MISC // +////////// + +TEST_F(AssemblerMIPS64Test, Bitswap) { + DriverStr(RepeatRR(&mips64::Mips64Assembler::Bitswap, "bitswap ${reg1}, ${reg2}"), "bitswap"); +} + +TEST_F(AssemblerMIPS64Test, Dbitswap) { + DriverStr(RepeatRR(&mips64::Mips64Assembler::Dbitswap, "dbitswap ${reg1}, ${reg2}"), "dbitswap"); +} + +TEST_F(AssemblerMIPS64Test, Dsbh) { + DriverStr(RepeatRR(&mips64::Mips64Assembler::Dsbh, "dsbh ${reg1}, ${reg2}"), "dsbh"); +} + +TEST_F(AssemblerMIPS64Test, Dshd) { + DriverStr(RepeatRR(&mips64::Mips64Assembler::Dshd, "dshd ${reg1}, ${reg2}"), "dshd"); +} + +TEST_F(AssemblerMIPS64Test, Wsbh) { + DriverStr(RepeatRR(&mips64::Mips64Assembler::Wsbh, "wsbh ${reg1}, ${reg2}"), "wsbh"); +} + +TEST_F(AssemblerMIPS64Test, Sc) { + DriverStr(RepeatRRIb(&mips64::Mips64Assembler::Sc, -9, "sc ${reg1}, {imm}(${reg2})"), "sc"); +} + +TEST_F(AssemblerMIPS64Test, Scd) { + DriverStr(RepeatRRIb(&mips64::Mips64Assembler::Scd, -9, "scd ${reg1}, {imm}(${reg2})"), "scd"); +} + +TEST_F(AssemblerMIPS64Test, Ll) { + DriverStr(RepeatRRIb(&mips64::Mips64Assembler::Ll, -9, "ll ${reg1}, {imm}(${reg2})"), "ll"); +} + +TEST_F(AssemblerMIPS64Test, Lld) { + DriverStr(RepeatRRIb(&mips64::Mips64Assembler::Lld, -9, "lld ${reg1}, {imm}(${reg2})"), "lld"); +} + +TEST_F(AssemblerMIPS64Test, Rotr) { + DriverStr(RepeatRRIb(&mips64::Mips64Assembler::Rotr, 5, "rotr ${reg1}, ${reg2}, {imm}"), "rotr"); +} + +TEST_F(AssemblerMIPS64Test, Seleqz) { + DriverStr(RepeatRRR(&mips64::Mips64Assembler::Seleqz, "seleqz ${reg1}, ${reg2}, ${reg3}"), + "seleqz"); +} + +TEST_F(AssemblerMIPS64Test, Selnez) { + DriverStr(RepeatRRR(&mips64::Mips64Assembler::Selnez, "selnez ${reg1}, ${reg2}, ${reg3}"), + "selnez"); +} + +TEST_F(AssemblerMIPS64Test, Clz) { + DriverStr(RepeatRR(&mips64::Mips64Assembler::Clz, "clz ${reg1}, ${reg2}"), "clz"); +} + +TEST_F(AssemblerMIPS64Test, Clo) { + DriverStr(RepeatRR(&mips64::Mips64Assembler::Clo, "clo ${reg1}, ${reg2}"), "clo"); +} + +TEST_F(AssemblerMIPS64Test, Dclz) { + DriverStr(RepeatRR(&mips64::Mips64Assembler::Dclz, "dclz ${reg1}, ${reg2}"), "dclz"); +} + +TEST_F(AssemblerMIPS64Test, Dclo) { + DriverStr(RepeatRR(&mips64::Mips64Assembler::Dclo, "dclo ${reg1}, ${reg2}"), "dclo"); +} + +} // namespace art -- cgit v1.2.3-59-g8ed1b