From eb2c9dd52679d590428a33556f45fb49eaef5e0e Mon Sep 17 00:00:00 2001 From: Andra Danciu Date: Mon, 14 Sep 2020 13:22:40 +0000 Subject: X86: Implement VarHandle.getAndAdd intrinsic This commit implements VarHandle getAndAdd intrinsic. This also implied adding xadd instruction and tests for it. Test: art/test.py --host -r -t 712-varhandle-invocation --32 Test: m test-art-host-gtest Bug: 65872996 Change-Id: I84dd95ba6464c8a73ace03a13817147c7099677a --- compiler/utils/x86/assembler_x86.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'compiler/utils/x86/assembler_x86.h') diff --git a/compiler/utils/x86/assembler_x86.h b/compiler/utils/x86/assembler_x86.h index c5469270e4..1c4f82663e 100644 --- a/compiler/utils/x86/assembler_x86.h +++ b/compiler/utils/x86/assembler_x86.h @@ -817,6 +817,10 @@ class X86Assembler final : public Assembler { void cmpxchgl(const Address& address, Register reg); void cmpxchg8b(const Address& address); + void xaddb(const Address& address, ByteRegister reg); + void xaddw(const Address& address, Register reg); + void xaddl(const Address& address, Register reg); + void mfence(); X86Assembler* fs(); @@ -859,6 +863,30 @@ class X86Assembler final : public Assembler { lock()->cmpxchg8b(address); } + void LockXaddb(const Address& address, Register reg) { + // For testing purpose + lock()->xaddb(address, static_cast(reg)); + } + + void LockXaddb(const Address& address, ByteRegister reg) { + lock()->xaddb(address, reg); + } + + void LockXaddw(const Address& address, Register reg) { + AssemblerBuffer::EnsureCapacity ensured(&buffer_); + // We make sure that the operand size override bytecode is emited before the lock bytecode. + // We test against clang which enforces this bytecode order. + EmitOperandSizeOverride(); + EmitUint8(0xF0); + EmitUint8(0x0F); + EmitUint8(0xC1); + EmitOperand(reg, address); + } + + void LockXaddl(const Address& address, Register reg) { + lock()->xaddl(address, reg); + } + // // Misc. functionality // -- cgit v1.2.3-59-g8ed1b