From 21c580bf3f024f3f02d627013fba18a4b4f855d5 Mon Sep 17 00:00:00 2001 From: Aart Bik Date: Mon, 13 Mar 2017 11:52:07 -0700 Subject: SIMD and-not for x86/x86_64 Rationale: Break-out CL of ART Vectorizer. Enables and-not optimization. Bug: 34083438 Test: assembler_x86[_64]_test Change-Id: I8fa61d88f9f014973b0d9707d39be56a7f995db8 --- compiler/utils/x86/assembler_x86.cc | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'compiler/utils/x86/assembler_x86.cc') diff --git a/compiler/utils/x86/assembler_x86.cc b/compiler/utils/x86/assembler_x86.cc index 6a57f45e42..0a6ceefe69 100644 --- a/compiler/utils/x86/assembler_x86.cc +++ b/compiler/utils/x86/assembler_x86.cc @@ -1169,6 +1169,32 @@ void X86Assembler::pand(XmmRegister dst, XmmRegister src) { } +void X86Assembler::andnpd(XmmRegister dst, XmmRegister src) { + AssemblerBuffer::EnsureCapacity ensured(&buffer_); + EmitUint8(0x66); + EmitUint8(0x0F); + EmitUint8(0x55); + EmitXmmRegisterOperand(dst, src); +} + + +void X86Assembler::andnps(XmmRegister dst, XmmRegister src) { + AssemblerBuffer::EnsureCapacity ensured(&buffer_); + EmitUint8(0x0F); + EmitUint8(0x55); + EmitXmmRegisterOperand(dst, src); +} + + +void X86Assembler::pandn(XmmRegister dst, XmmRegister src) { + AssemblerBuffer::EnsureCapacity ensured(&buffer_); + EmitUint8(0x66); + EmitUint8(0x0F); + EmitUint8(0xDF); + EmitXmmRegisterOperand(dst, src); +} + + void X86Assembler::orpd(XmmRegister dst, XmmRegister src) { AssemblerBuffer::EnsureCapacity ensured(&buffer_); EmitUint8(0x66); -- cgit v1.2.3-59-g8ed1b