From 5141763acd9ca2ddb2ee6bcc742d6d2a2aebd7df Mon Sep 17 00:00:00 2001
From: Chris Larsen <chris.larsen@imgtec.com>
Date: Fri, 2 Oct 2015 13:24:25 -0700
Subject: MIPS64: Additional assember tests:

- MOV.fmt       - NEG.fmt       - CVT.D.fmt     - CVT.S.fmt
- JALR          - SLL           - SRL           - SRA
- DSLL          - DSRA          - DSRL          - DSLL32
- DSRL32        - DSRA32

Change-Id: Ib15ac72128805a9bca707211359191e32d95d5d7
---
 compiler/utils/mips64/assembler_mips64.cc | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'compiler/utils/mips64/assembler_mips64.cc')

diff --git a/compiler/utils/mips64/assembler_mips64.cc b/compiler/utils/mips64/assembler_mips64.cc
index b078f3e4cf..7b4e6a3044 100644
--- a/compiler/utils/mips64/assembler_mips64.cc
+++ b/compiler/utils/mips64/assembler_mips64.cc
@@ -773,6 +773,10 @@ void Mips64Assembler::Cvtds(FpuRegister fd, FpuRegister fs) {
   EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x21);
 }
 
+void Mips64Assembler::Cvtsl(FpuRegister fd, FpuRegister fs) {
+  EmitFR(0x11, 0x15, static_cast<FpuRegister>(0), fs, fd, 0x20);
+}
+
 void Mips64Assembler::Cvtdl(FpuRegister fd, FpuRegister fs) {
   EmitFR(0x11, 0x15, static_cast<FpuRegister>(0), fs, fd, 0x21);
 }
-- 
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