From 4147fcc43c2ee019a06e55384985e3eaf82dcb8c Mon Sep 17 00:00:00 2001 From: Alexey Frunze Date: Sat, 17 Jun 2017 19:57:27 -0700 Subject: MIPS: Reduce Baker read barrier code size overhead Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-gtest Test: testrunner.py --target --optimizing Test: same tests as above on CI20 Test: booted MIPS32 and MIPS64 in QEMU with poisoning in configurations: - with Baker read barrier thunks - without Baker read barrier thunks - ART_READ_BARRIER_TYPE=TABLELOOKUP Change-Id: I79f320bf8862a04215c76cfeff3118ebc87f7ef2 --- compiler/utils/mips64/assembler_mips64.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'compiler/utils/mips64/assembler_mips64.cc') diff --git a/compiler/utils/mips64/assembler_mips64.cc b/compiler/utils/mips64/assembler_mips64.cc index 24900a7f10..90398540f8 100644 --- a/compiler/utils/mips64/assembler_mips64.cc +++ b/compiler/utils/mips64/assembler_mips64.cc @@ -795,6 +795,10 @@ void Mips64Assembler::Bc1nez(FpuRegister ft, uint16_t imm16) { EmitFI(0x11, 0xD, ft, imm16); } +void Mips64Assembler::Beqz(GpuRegister rt, uint16_t imm16) { + EmitI(0x4, ZERO, rt, imm16); +} + void Mips64Assembler::EmitBcondc(BranchCondition cond, GpuRegister rs, GpuRegister rt, -- cgit v1.2.3-59-g8ed1b