From 51765b098301fff1897361b2d1a21af356d9d6d8 Mon Sep 17 00:00:00 2001
From: Lena Djokic <Lena.Djokic@imgtec.com>
Date: Thu, 22 Jun 2017 13:49:59 +0200
Subject: MIPS32: ART Vectorizer

MIPS32 implementation which uses MSA extension.

Note: Testing is done with checker parts of tests 640, 645, 646 and
      651, locally changed to cover MIPS32 cases. These changes can't
      be included in this patch since MSA is not a default option.

Test: ./testrunner.py --target --optimizing -j1 in QEMU (mips32r6)
Change-Id: Ieba28f94c48c943d5444017bede9a5d409149762
---
 compiler/utils/mips/assembler_mips.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'compiler/utils/mips/assembler_mips.h')

diff --git a/compiler/utils/mips/assembler_mips.h b/compiler/utils/mips/assembler_mips.h
index a229882d18..33803bb576 100644
--- a/compiler/utils/mips/assembler_mips.h
+++ b/compiler/utils/mips/assembler_mips.h
@@ -612,6 +612,9 @@ class MipsAssembler FINAL : public Assembler, public JNIMacroAssembler<PointerSi
   void IlvrW(VectorRegister wd, VectorRegister ws, VectorRegister wt);
   void IlvrD(VectorRegister wd, VectorRegister ws, VectorRegister wt);
 
+  // Helper for replicating floating point value in all destination elements.
+  void ReplicateFPToVectorRegister(VectorRegister dst, FRegister src, bool is_double);
+
   // Higher level composite instructions.
   void LoadConst32(Register rd, int32_t value);
   void LoadConst64(Register reg_hi, Register reg_lo, int64_t value);
-- 
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