From 4147fcc43c2ee019a06e55384985e3eaf82dcb8c Mon Sep 17 00:00:00 2001 From: Alexey Frunze Date: Sat, 17 Jun 2017 19:57:27 -0700 Subject: MIPS: Reduce Baker read barrier code size overhead Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-gtest Test: testrunner.py --target --optimizing Test: same tests as above on CI20 Test: booted MIPS32 and MIPS64 in QEMU with poisoning in configurations: - with Baker read barrier thunks - without Baker read barrier thunks - ART_READ_BARRIER_TYPE=TABLELOOKUP Change-Id: I79f320bf8862a04215c76cfeff3118ebc87f7ef2 --- compiler/utils/mips/assembler_mips.cc | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'compiler/utils/mips/assembler_mips.cc') diff --git a/compiler/utils/mips/assembler_mips.cc b/compiler/utils/mips/assembler_mips.cc index c581f1c58f..24e34508d1 100644 --- a/compiler/utils/mips/assembler_mips.cc +++ b/compiler/utils/mips/assembler_mips.cc @@ -828,6 +828,22 @@ void MipsAssembler::Aui(Register rt, Register rs, uint16_t imm16) { DsFsmInstrRrr(EmitI(0xf, rs, rt, imm16), rt, rt, rs); } +void MipsAssembler::AddUpper(Register rt, Register rs, uint16_t imm16, Register tmp) { + bool increment = (rs == rt); + if (increment) { + CHECK_NE(rs, tmp); + } + if (IsR6()) { + Aui(rt, rs, imm16); + } else if (increment) { + Lui(tmp, imm16); + Addu(rt, rs, tmp); + } else { + Lui(rt, imm16); + Addu(rt, rs, rt); + } +} + void MipsAssembler::Sync(uint32_t stype) { DsFsmInstrNop(EmitR(0, ZERO, ZERO, ZERO, stype & 0x1f, 0xf)); } -- cgit v1.2.3-59-g8ed1b