From 3309c01e55821f693e3b9cec0ef24969edf2528f Mon Sep 17 00:00:00 2001 From: Lena Djokic Date: Fri, 13 Oct 2017 14:34:32 +0200 Subject: MIPS: Introduce a few MSA instructions These instructions are needed for SIMD reduction. Also added assembler tests for each instruction. Test: mma test-art-host-gtest Change-Id: I0f02618a14b4cbcc3b81ce51dd2586fa4cdbfd18 --- compiler/utils/mips/assembler_mips.cc | 212 ++++++++++++++++++++++++++++++++++ 1 file changed, 212 insertions(+) (limited to 'compiler/utils/mips/assembler_mips.cc') diff --git a/compiler/utils/mips/assembler_mips.cc b/compiler/utils/mips/assembler_mips.cc index e85645b446..cbb2c0ea47 100644 --- a/compiler/utils/mips/assembler_mips.cc +++ b/compiler/utils/mips/assembler_mips.cc @@ -2800,6 +2800,74 @@ void MipsAssembler::SplatiD(VectorRegister wd, VectorRegister ws, int n1) { static_cast(ws)); } +void MipsAssembler::Copy_sB(Register rd, VectorRegister ws, int n4) { + CHECK(HasMsa()); + CHECK(IsUint<4>(n4)) << n4; + DsFsmInstrRf(EmitMsaELM(0x2, n4 | kMsaDfNByteMask, ws, static_cast(rd), 0x19), + rd, + static_cast(ws)); +} + +void MipsAssembler::Copy_sH(Register rd, VectorRegister ws, int n3) { + CHECK(HasMsa()); + CHECK(IsUint<3>(n3)) << n3; + DsFsmInstrRf(EmitMsaELM(0x2, n3 | kMsaDfNHalfwordMask, ws, static_cast(rd), 0x19), + rd, + static_cast(ws)); +} + +void MipsAssembler::Copy_sW(Register rd, VectorRegister ws, int n2) { + CHECK(HasMsa()); + CHECK(IsUint<2>(n2)) << n2; + DsFsmInstrRf(EmitMsaELM(0x2, n2 | kMsaDfNWordMask, ws, static_cast(rd), 0x19), + rd, + static_cast(ws)); +} + +void MipsAssembler::Copy_uB(Register rd, VectorRegister ws, int n4) { + CHECK(HasMsa()); + CHECK(IsUint<4>(n4)) << n4; + DsFsmInstrRf(EmitMsaELM(0x3, n4 | kMsaDfNByteMask, ws, static_cast(rd), 0x19), + rd, + static_cast(ws)); +} + +void MipsAssembler::Copy_uH(Register rd, VectorRegister ws, int n3) { + CHECK(HasMsa()); + CHECK(IsUint<3>(n3)) << n3; + DsFsmInstrRf(EmitMsaELM(0x3, n3 | kMsaDfNHalfwordMask, ws, static_cast(rd), 0x19), + rd, + static_cast(ws)); +} + +void MipsAssembler::InsertB(VectorRegister wd, Register rs, int n4) { + CHECK(HasMsa()); + CHECK(IsUint<4>(n4)) << n4; + DsFsmInstrFffr(EmitMsaELM(0x4, n4 | kMsaDfNByteMask, static_cast(rs), wd, 0x19), + static_cast(wd), + static_cast(wd), + rs); +} + +void MipsAssembler::InsertH(VectorRegister wd, Register rs, int n3) { + CHECK(HasMsa()); + CHECK(IsUint<3>(n3)) << n3; + DsFsmInstrFffr( + EmitMsaELM(0x4, n3 | kMsaDfNHalfwordMask, static_cast(rs), wd, 0x19), + static_cast(wd), + static_cast(wd), + rs); +} + +void MipsAssembler::InsertW(VectorRegister wd, Register rs, int n2) { + CHECK(HasMsa()); + CHECK(IsUint<2>(n2)) << n2; + DsFsmInstrFffr(EmitMsaELM(0x4, n2 | kMsaDfNWordMask, static_cast(rs), wd, 0x19), + static_cast(wd), + static_cast(wd), + rs); +} + void MipsAssembler::FillB(VectorRegister wd, Register rs) { CHECK(HasMsa()); DsFsmInstrFr(EmitMsa2R(0xc0, 0x0, static_cast(rs), wd, 0x1e), @@ -2921,6 +2989,38 @@ void MipsAssembler::StD(VectorRegister wd, Register rs, int offset) { rs); } +void MipsAssembler::IlvlB(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x4, 0x0, wt, ws, wd, 0x14), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + +void MipsAssembler::IlvlH(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x4, 0x1, wt, ws, wd, 0x14), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + +void MipsAssembler::IlvlW(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x4, 0x2, wt, ws, wd, 0x14), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + +void MipsAssembler::IlvlD(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x4, 0x3, wt, ws, wd, 0x14), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + void MipsAssembler::IlvrB(VectorRegister wd, VectorRegister ws, VectorRegister wt) { CHECK(HasMsa()); DsFsmInstrFff(EmitMsa3R(0x5, 0x0, wt, ws, wd, 0x14), @@ -2953,6 +3053,70 @@ void MipsAssembler::IlvrD(VectorRegister wd, VectorRegister ws, VectorRegister w static_cast(wt)); } +void MipsAssembler::IlvevB(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x6, 0x0, wt, ws, wd, 0x14), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + +void MipsAssembler::IlvevH(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x6, 0x1, wt, ws, wd, 0x14), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + +void MipsAssembler::IlvevW(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x6, 0x2, wt, ws, wd, 0x14), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + +void MipsAssembler::IlvevD(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x6, 0x3, wt, ws, wd, 0x14), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + +void MipsAssembler::IlvodB(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x7, 0x0, wt, ws, wd, 0x14), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + +void MipsAssembler::IlvodH(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x7, 0x1, wt, ws, wd, 0x14), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + +void MipsAssembler::IlvodW(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x7, 0x2, wt, ws, wd, 0x14), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + +void MipsAssembler::IlvodD(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x7, 0x3, wt, ws, wd, 0x14), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + void MipsAssembler::MaddvB(VectorRegister wd, VectorRegister ws, VectorRegister wt) { CHECK(HasMsa()); DsFsmInstrFff(EmitMsa3R(0x1, 0x0, wt, ws, wd, 0x12), @@ -3049,6 +3213,54 @@ void MipsAssembler::FmsubD(VectorRegister wd, VectorRegister ws, VectorRegister static_cast(wt)); } +void MipsAssembler::Hadd_sH(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x4, 0x1, wt, ws, wd, 0x15), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + +void MipsAssembler::Hadd_sW(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x4, 0x2, wt, ws, wd, 0x15), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + +void MipsAssembler::Hadd_sD(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x4, 0x3, wt, ws, wd, 0x15), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + +void MipsAssembler::Hadd_uH(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x5, 0x1, wt, ws, wd, 0x15), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + +void MipsAssembler::Hadd_uW(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x5, 0x2, wt, ws, wd, 0x15), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + +void MipsAssembler::Hadd_uD(VectorRegister wd, VectorRegister ws, VectorRegister wt) { + CHECK(HasMsa()); + DsFsmInstrFff(EmitMsa3R(0x5, 0x3, wt, ws, wd, 0x15), + static_cast(wd), + static_cast(ws), + static_cast(wt)); +} + void MipsAssembler::ReplicateFPToVectorRegister(VectorRegister dst, FRegister src, bool is_double) { -- cgit v1.2.3-59-g8ed1b