From 51aff3a6564303cab0b7ac82495b4e2e349c6ff3 Mon Sep 17 00:00:00 2001 From: Alexey Frunze Date: Thu, 17 Mar 2016 17:21:45 -0700 Subject: MIPS32: Implement UnsafeCASInt and UnsafeCASObject intrinsics. Change-Id: Ie871763b9a36075fd3d70ee6e2e241ae1ccc36cf --- compiler/utils/mips/assembler_mips.cc | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'compiler/utils/mips/assembler_mips.cc') diff --git a/compiler/utils/mips/assembler_mips.cc b/compiler/utils/mips/assembler_mips.cc index 7c41813457..a1798c0f70 100644 --- a/compiler/utils/mips/assembler_mips.cc +++ b/compiler/utils/mips/assembler_mips.cc @@ -485,6 +485,28 @@ void MipsAssembler::Swr(Register rt, Register rs, uint16_t imm16) { EmitI(0x2e, rs, rt, imm16); } +void MipsAssembler::LlR2(Register rt, Register base, int16_t imm16) { + CHECK(!IsR6()); + EmitI(0x30, base, rt, imm16); +} + +void MipsAssembler::ScR2(Register rt, Register base, int16_t imm16) { + CHECK(!IsR6()); + EmitI(0x38, base, rt, imm16); +} + +void MipsAssembler::LlR6(Register rt, Register base, int16_t imm9) { + CHECK(IsR6()); + CHECK(IsInt<9>(imm9)); + EmitI(0x1f, base, rt, ((imm9 & 0x1ff) << 7) | 0x36); +} + +void MipsAssembler::ScR6(Register rt, Register base, int16_t imm9) { + CHECK(IsR6()); + CHECK(IsInt<9>(imm9)); + EmitI(0x1f, base, rt, ((imm9 & 0x1ff) << 7) | 0x26); +} + void MipsAssembler::Slt(Register rd, Register rs, Register rt) { EmitR(0, rs, rt, rd, 0, 0x2a); } -- cgit v1.2.3-59-g8ed1b