From 1b8464d17c2266763714ae18be7c4dc26e28bf61 Mon Sep 17 00:00:00 2001 From: Alexey Frunze Date: Sat, 12 Nov 2016 17:22:05 -0800 Subject: MIPS32: Pass more arguments in registers. Specifically, use A0-A3,T0-T1 for non-floats and F8-F19 for floats. Test: booted MIPS32R2 in QEMU Test: test-art-target-run-test-optimizing (MIPS32R2) on CI20 Test: test-art-target-gtest (MIPS32R2) on CI20 Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-run-test-optimizing (MIPS32R6) in QEMU Test: test-art-target-gtest (MIPS32R6) in QEMU Test: test-art-host-gtest Change-Id: Ib8b0310a109d9f3d70119c1e605e54b013e60728 --- compiler/utils/mips/assembler_mips.cc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'compiler/utils/mips/assembler_mips.cc') diff --git a/compiler/utils/mips/assembler_mips.cc b/compiler/utils/mips/assembler_mips.cc index b29974c238..3dcad6a6b9 100644 --- a/compiler/utils/mips/assembler_mips.cc +++ b/compiler/utils/mips/assembler_mips.cc @@ -3252,6 +3252,9 @@ void MipsAssembler::EmitLoad(ManagedRegister m_dst, Register src_register, int32 CHECK_EQ(kMipsDoublewordSize, size) << dst; LoadDFromOffset(dst.AsFRegister(), src_register, src_offset); } + } else if (dst.IsDRegister()) { + CHECK_EQ(kMipsDoublewordSize, size) << dst; + LoadDFromOffset(dst.AsOverlappingDRegisterLow(), src_register, src_offset); } } @@ -3396,6 +3399,9 @@ void MipsAssembler::Store(FrameOffset dest, ManagedRegister msrc, size_t size) { CHECK_EQ(kMipsDoublewordSize, size); StoreDToOffset(src.AsFRegister(), SP, dest.Int32Value()); } + } else if (src.IsDRegister()) { + CHECK_EQ(kMipsDoublewordSize, size); + StoreDToOffset(src.AsOverlappingDRegisterLow(), SP, dest.Int32Value()); } } -- cgit v1.2.3-59-g8ed1b