From 6d729a789d3d7771e13d9445ee0be1d9d48a81b5 Mon Sep 17 00:00:00 2001 From: Roland Levillain Date: Fri, 30 Jun 2017 18:34:01 +0100 Subject: Introduce a Marking Register in ARM code generation. When generating code for ARM, maintain the status of Thread::Current()->GetIsGcMarking() in register R8, dubbed MR (Marking Register), and check the value of that register (instead of loading and checking a read barrier marking entrypoint) in read barriers. Test: m test-art-target Test: m test-art-target with tree built with ART_USE_READ_BARRIER=false Test: m test-art-host-gtest Test: ARM device boot test Bug: 37707231 Change-Id: I30b44254460d0bbb9f1b2adc65eca52ca3de3f53 --- compiler/utils/assembler_thumb_test.cc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'compiler/utils/assembler_thumb_test.cc') diff --git a/compiler/utils/assembler_thumb_test.cc b/compiler/utils/assembler_thumb_test.cc index 4e9b619979..759ed38601 100644 --- a/compiler/utils/assembler_thumb_test.cc +++ b/compiler/utils/assembler_thumb_test.cc @@ -1643,6 +1643,10 @@ void EmitAndCheck(JniAssemblerType* assembler, const char* testname) { #define __ assembler. TEST_F(ArmVIXLAssemblerTest, VixlJniHelpers) { + // Run the test only with Baker read barriers, as the expected + // generated code contains a Marking Register refresh instruction. + TEST_DISABLED_WITHOUT_BAKER_READ_BARRIERS(); + const bool is_static = true; const bool is_synchronized = false; const bool is_critical_native = false; -- cgit v1.2.3-59-g8ed1b