From eee1c0ec2b08a6be642b329dc2fe885391127da3 Mon Sep 17 00:00:00 2001 From: Vladimir Marko Date: Fri, 21 Apr 2017 17:58:41 +0100 Subject: ARM: Link-time generated thunks for Baker CC read barrier. Remaining work for follow-up CLs: - use implicit null check in field thunk, - use 16-bit LDRs for fields and GC roots. Test: m test-art-target-gtest Test: testrunner.py --target on Nexus 6P. Test: testrunner.py --target on Nexus 6P with heap poisoning enabled. Test: Repeat the above tests with ART_USE_OLD_ARM_BACKEND=true. Bug: 29516974 Bug: 30126666 Bug: 36141117 Change-Id: Iad5addab72d790a9d61879f61f2e75b246bcdf5a --- compiler/utils/arm/assembler_arm.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'compiler/utils/arm/assembler_arm.h') diff --git a/compiler/utils/arm/assembler_arm.h b/compiler/utils/arm/assembler_arm.h index 0ed8a35338..0f24e81be2 100644 --- a/compiler/utils/arm/assembler_arm.h +++ b/compiler/utils/arm/assembler_arm.h @@ -652,6 +652,9 @@ class ArmAssembler : public Assembler { virtual void blx(Register rm, Condition cond = AL) = 0; virtual void bx(Register rm, Condition cond = AL) = 0; + // ADR instruction loading register for branching to the label. + virtual void AdrCode(Register rt, Label* label) = 0; + // Memory barriers. virtual void dmb(DmbOptions flavor) = 0; -- cgit v1.2.3-59-g8ed1b