From af24def8967027f10ce8d44cb209c23032a2a1b4 Mon Sep 17 00:00:00 2001 From: Roland Levillain Date: Wed, 12 Jul 2017 13:18:01 +0100 Subject: Fix ART ARM64 CFI gtests with GCs other than CC with Baker read barriers. Since the introduction of a Marking Register in the ARM64 back end, gtests jni_cfi_test and optimizing_cfi_test produce different outputs for the Concurrent Copying (CC) collector with Baker read barriers on the one hand, and for other GCs on the other hand. Test: m test-art-host-gtest with tree built with ART_USE_READ_BARRIER=false Bug: 37707231 Change-Id: I63de8873f52df593eb664970f2be20f1089804a9 --- compiler/optimizing/optimizing_cfi_test.cc | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'compiler/optimizing') diff --git a/compiler/optimizing/optimizing_cfi_test.cc b/compiler/optimizing/optimizing_cfi_test.cc index 490e50cb77..f59bfb610c 100644 --- a/compiler/optimizing/optimizing_cfi_test.cc +++ b/compiler/optimizing/optimizing_cfi_test.cc @@ -171,18 +171,31 @@ class OptimizingCFITest : public CFITest { #ifdef ART_ENABLE_CODEGEN_arm TEST_ISA(kThumb2) #endif + #ifdef ART_ENABLE_CODEGEN_arm64 +// Run the tests for ARM64 only with Baker read barriers, as the +// expected generated code saves and restore X21 and X22 (instead of +// X20 and X21), as X20 is used as Marking Register in the Baker read +// barrier configuration, and as such is removed from the set of +// callee-save registers in the ARM64 code generator of the Optimizing +// compiler. +#if defined(USE_READ_BARRIER) && defined(USE_BAKER_READ_BARRIER) TEST_ISA(kArm64) #endif +#endif + #ifdef ART_ENABLE_CODEGEN_x86 TEST_ISA(kX86) #endif + #ifdef ART_ENABLE_CODEGEN_x86_64 TEST_ISA(kX86_64) #endif + #ifdef ART_ENABLE_CODEGEN_mips TEST_ISA(kMips) #endif + #ifdef ART_ENABLE_CODEGEN_mips64 TEST_ISA(kMips64) #endif -- cgit v1.2.3-59-g8ed1b