From 5576f3741c58cb8b5fb2f68f3b3a9415efe05f4f Mon Sep 17 00:00:00 2001 From: Aart Bik Date: Thu, 23 Mar 2017 16:17:37 -0700 Subject: Implement a SIMD spilling slot. Rationale: The last ART vectorizer break-out CL \O/ This ensures spilling on x86 and x86_4 is correct. Also, it paves the way to wider SIMD on ARM and MIPS. Test: test-art-host Bug: 34083438 Change-Id: I5b27d18c2045f3ab70b64c335423b3ff2a507ac2 --- compiler/optimizing/ssa_liveness_analysis.cc | 3 +++ 1 file changed, 3 insertions(+) (limited to 'compiler/optimizing/ssa_liveness_analysis.cc') diff --git a/compiler/optimizing/ssa_liveness_analysis.cc b/compiler/optimizing/ssa_liveness_analysis.cc index c0a045c33e..36ee5a903a 100644 --- a/compiler/optimizing/ssa_liveness_analysis.cc +++ b/compiler/optimizing/ssa_liveness_analysis.cc @@ -470,6 +470,8 @@ bool LiveInterval::SameRegisterKind(Location other) const { } size_t LiveInterval::NumberOfSpillSlotsNeeded() const { + // TODO: detect vector operation. + // Return number of needed spill slots based on type. return (type_ == Primitive::kPrimLong || type_ == Primitive::kPrimDouble) ? 2 : 1; } @@ -497,6 +499,7 @@ Location LiveInterval::ToLocation() const { switch (NumberOfSpillSlotsNeeded()) { case 1: return Location::StackSlot(GetParent()->GetSpillSlot()); case 2: return Location::DoubleStackSlot(GetParent()->GetSpillSlot()); + case 4: return Location::SIMDStackSlot(GetParent()->GetSpillSlot()); default: LOG(FATAL) << "Unexpected number of spill slots"; UNREACHABLE(); } } else { -- cgit v1.2.3-59-g8ed1b