From cfa59b49cde265dc5329a7e6956445f9f7a75f15 Mon Sep 17 00:00:00 2001 From: Aart Bik Date: Thu, 31 Aug 2017 09:08:13 -0700 Subject: Basic SIMD reduction support. Rationale: Enables vectorization of x += .... for very basic (simple, same-type) constructs. Paves the way for more complex (narrower and/or mixed-type) constructs, which will be handled by the next CL. This is a revert^2 of I7880c135aee3ed0a39da9ae5b468cbf80e613766 and thus a revert of I1c1c87b6323e01442e8fbd94869ddc9e760ea1fc PS1-2 shows what needed to change, with regression tests Test: test-art-host test-art-target Bug: 64091002, 65212948 Change-Id: I2454778dd0ef1da915c178c7274e1cf33e271d0f --- compiler/optimizing/scheduler_arm64.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'compiler/optimizing/scheduler_arm64.h') diff --git a/compiler/optimizing/scheduler_arm64.h b/compiler/optimizing/scheduler_arm64.h index 63d5b7d6b6..e1a80ec6fb 100644 --- a/compiler/optimizing/scheduler_arm64.h +++ b/compiler/optimizing/scheduler_arm64.h @@ -83,8 +83,8 @@ class SchedulingLatencyVisitorARM64 : public SchedulingLatencyVisitor { M(SuspendCheck , unused) \ M(TypeConversion , unused) \ M(VecReplicateScalar , unused) \ - M(VecSetScalars , unused) \ - M(VecSumReduce , unused) \ + M(VecExtractScalar , unused) \ + M(VecReduce , unused) \ M(VecCnv , unused) \ M(VecNeg , unused) \ M(VecAbs , unused) \ @@ -103,6 +103,7 @@ class SchedulingLatencyVisitorARM64 : public SchedulingLatencyVisitor { M(VecShl , unused) \ M(VecShr , unused) \ M(VecUShr , unused) \ + M(VecSetScalars , unused) \ M(VecMultiplyAccumulate, unused) \ M(VecLoad , unused) \ M(VecStore , unused) -- cgit v1.2.3-59-g8ed1b