From d97dc40d186aec46bfd318b6a2026a98241d7e9c Mon Sep 17 00:00:00 2001
From: Nicolas Geoffray <ngeoffray@google.com>
Date: Thu, 22 Jan 2015 13:50:01 +0000
Subject: Support callee save floating point registers on x64.

- Share the computation of core_spill_mask and fpu_spill_mask
  between backends.
- Remove explicit stack overflow check support: we need to adjust
  them and since they are not tested, they will easily bitrot.

Change-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a
---
 compiler/optimizing/optimizing_compiler.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'compiler/optimizing/optimizing_compiler.cc')

diff --git a/compiler/optimizing/optimizing_compiler.cc b/compiler/optimizing/optimizing_compiler.cc
index 1e0d65a945..5bca73003e 100644
--- a/compiler/optimizing/optimizing_compiler.cc
+++ b/compiler/optimizing/optimizing_compiler.cc
@@ -286,7 +286,7 @@ CompiledMethod* OptimizingCompiler::CompileOptimized(HGraph* graph,
       ArrayRef<const uint8_t>(allocator.GetMemory()),
       codegen->GetFrameSize(),
       codegen->GetCoreSpillMask(),
-      0, /* FPR spill mask, unused */
+      codegen->GetFpuSpillMask(),
       ArrayRef<const uint8_t>(stack_map));
 }
 
@@ -313,7 +313,7 @@ CompiledMethod* OptimizingCompiler::CompileBaseline(
                                                  ArrayRef<const uint8_t>(allocator.GetMemory()),
                                                  codegen->GetFrameSize(),
                                                  codegen->GetCoreSpillMask(),
-                                                 0, /* FPR spill mask, unused */
+                                                 codegen->GetFpuSpillMask(),
                                                  &src_mapping_table,
                                                  AlignVectorSize(mapping_table),
                                                  AlignVectorSize(vmap_table),
-- 
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