From 8ba4de1a5684686447a578bdc425321fd3bccca6 Mon Sep 17 00:00:00 2001 From: Artem Serov Date: Wed, 4 Dec 2019 21:10:23 +0000 Subject: ART: Implement predicated SIMD vectorization. This CL brings support for predicated execution for auto-vectorizer and implements arm64 SVE vector backend. This version passes all the VIXL simulator-runnable tests in SVE mode with checker off (as all VecOp CHECKs need to be adjusted for an extra input) and all tests in NEON mode. Test: art SIMD tests on VIXL simulator. Test: art tests on FVP (steps in test/README.arm_fvp.md) Change-Id: Ib78bde31a15e6713d875d6668ad4458f5519605f --- compiler/optimizing/nodes_vector.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'compiler/optimizing/nodes_vector.h') diff --git a/compiler/optimizing/nodes_vector.h b/compiler/optimizing/nodes_vector.h index 9c6b422c87..a2cd86dc33 100644 --- a/compiler/optimizing/nodes_vector.h +++ b/compiler/optimizing/nodes_vector.h @@ -145,6 +145,15 @@ class HVecOperation : public HVariableInputSizeInstruction { return pred_input->AsVecPredSetOperation(); } + // Returns whether two vector operations are predicated by the same vector predicate + // with the same predication type. + static bool HaveSamePredicate(HVecOperation* instr0, HVecOperation* instr1) { + HVecPredSetOperation* instr0_predicate = instr0->GetGoverningPredicate(); + HVecOperation::PredicationKind instr0_predicate_kind = instr0->GetPredicationKind(); + return instr1->GetGoverningPredicate() == instr0_predicate && + instr1->GetPredicationKind() == instr0_predicate_kind; + } + // Returns the number of elements packed in a vector. size_t GetVectorLength() const { return vector_length_; -- cgit v1.2.3-59-g8ed1b