From 97c46466aea25ab63a99b3d1afc558f0d9f55abb Mon Sep 17 00:00:00 2001 From: Roland Levillain Date: Thu, 11 May 2017 14:04:03 +0100 Subject: Introduce a Marking Register in ARM64 code generation. When generating code for ARM64, maintain the status of Thread::Current()->GetIsGcMarking() in register X20, dubbed MR (Marking Register), and check the value of that register (instead of loading and checking a read barrier marking entrypoint) in read barriers. Test: m test-art-target Test: m test-art-target with tree built with ART_USE_READ_BARRIER=false Test: ARM64 device boot test Bug: 37707231 Change-Id: Ibe9bc5c99a2176b0a0476e9e9ad7fcc9f745017b --- compiler/optimizing/intrinsics_x86.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'compiler/optimizing/intrinsics_x86.cc') diff --git a/compiler/optimizing/intrinsics_x86.cc b/compiler/optimizing/intrinsics_x86.cc index 6b4851d541..a18b0cc400 100644 --- a/compiler/optimizing/intrinsics_x86.cc +++ b/compiler/optimizing/intrinsics_x86.cc @@ -143,8 +143,7 @@ class ReadBarrierSystemArrayCopySlowPathX86 : public SlowPathCode { // explanations.) DCHECK_NE(temp2, ESP); DCHECK(0 <= temp2 && temp2 < kNumberOfCpuRegisters) << temp2; - int32_t entry_point_offset = - CodeGenerator::GetReadBarrierMarkEntryPointsOffset(temp2); + int32_t entry_point_offset = Thread::ReadBarrierMarkEntryPointsOffset(temp2); // This runtime call does not require a stack map. x86_codegen->InvokeRuntimeWithoutRecordingPcInfo(entry_point_offset, instruction_, this); __ MaybePoisonHeapReference(temp2); -- cgit v1.2.3-59-g8ed1b