From 97c46466aea25ab63a99b3d1afc558f0d9f55abb Mon Sep 17 00:00:00 2001 From: Roland Levillain Date: Thu, 11 May 2017 14:04:03 +0100 Subject: Introduce a Marking Register in ARM64 code generation. When generating code for ARM64, maintain the status of Thread::Current()->GetIsGcMarking() in register X20, dubbed MR (Marking Register), and check the value of that register (instead of loading and checking a read barrier marking entrypoint) in read barriers. Test: m test-art-target Test: m test-art-target with tree built with ART_USE_READ_BARRIER=false Test: ARM64 device boot test Bug: 37707231 Change-Id: Ibe9bc5c99a2176b0a0476e9e9ad7fcc9f745017b --- compiler/optimizing/intrinsics_arm.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'compiler/optimizing/intrinsics_arm.cc') diff --git a/compiler/optimizing/intrinsics_arm.cc b/compiler/optimizing/intrinsics_arm.cc index ae5f8d1760..37958660e1 100644 --- a/compiler/optimizing/intrinsics_arm.cc +++ b/compiler/optimizing/intrinsics_arm.cc @@ -154,8 +154,7 @@ class ReadBarrierSystemArrayCopySlowPathARM : public SlowPathCode { DCHECK(0 <= tmp && tmp < kNumberOfCoreRegisters) << tmp; // TODO: Load the entrypoint once before the loop, instead of // loading it at every iteration. - int32_t entry_point_offset = - CodeGenerator::GetReadBarrierMarkEntryPointsOffset(tmp); + int32_t entry_point_offset = Thread::ReadBarrierMarkEntryPointsOffset(tmp); // This runtime call does not require a stack map. arm_codegen->InvokeRuntimeWithoutRecordingPcInfo(entry_point_offset, instruction_, this); __ MaybePoisonHeapReference(tmp); -- cgit v1.2.3-59-g8ed1b