From 74234daabb28a4b9c804bf8bf908e7334bd4d400 Mon Sep 17 00:00:00 2001 From: Anton Kirilov Date: Fri, 13 Jan 2017 14:42:47 +0000 Subject: ARM: Merge data-processing instructions and shifts/(un)signed extensions This commit mirrors the work that has already been done for ARM64. Test: m test-art-target-run-test-551-checker-shifter-operand Change-Id: Iec8c1563b035f40f0e18dcffde28d91dc21922f8 --- .../optimizing/instruction_simplifier_shared.h | 27 ++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'compiler/optimizing/instruction_simplifier_shared.h') diff --git a/compiler/optimizing/instruction_simplifier_shared.h b/compiler/optimizing/instruction_simplifier_shared.h index 56804f5e90..83e3ffca57 100644 --- a/compiler/optimizing/instruction_simplifier_shared.h +++ b/compiler/optimizing/instruction_simplifier_shared.h @@ -21,6 +21,33 @@ namespace art { +namespace helpers { + +inline bool CanFitInShifterOperand(HInstruction* instruction) { + if (instruction->IsTypeConversion()) { + HTypeConversion* conversion = instruction->AsTypeConversion(); + Primitive::Type result_type = conversion->GetResultType(); + Primitive::Type input_type = conversion->GetInputType(); + // We don't expect to see the same type as input and result. + return Primitive::IsIntegralType(result_type) && Primitive::IsIntegralType(input_type) && + (result_type != input_type); + } else { + return (instruction->IsShl() && instruction->AsShl()->InputAt(1)->IsIntConstant()) || + (instruction->IsShr() && instruction->AsShr()->InputAt(1)->IsIntConstant()) || + (instruction->IsUShr() && instruction->AsUShr()->InputAt(1)->IsIntConstant()); + } +} + +inline bool HasShifterOperand(HInstruction* instr, InstructionSet isa) { + // On ARM64 `neg` instructions are an alias of `sub` using the zero register + // as the first register input. + bool res = instr->IsAdd() || instr->IsAnd() || (isa == kArm64 && instr->IsNeg()) || + instr->IsOr() || instr->IsSub() || instr->IsXor(); + return res; +} + +} // namespace helpers + bool TryCombineMultiplyAccumulate(HMul* mul, InstructionSet isa); // For bitwise operations (And/Or/Xor) with a negated input, try to use // a negated bitwise instruction. -- cgit v1.2.3-59-g8ed1b