From b658a268e2e76e429702c2929d24ebbbf909e947 Mon Sep 17 00:00:00 2001 From: Anton Romanov Date: Thu, 30 May 2024 17:05:54 +0500 Subject: riscv: Expand BitwiseNegatedRight to riscv64, optimize Add BitwiseNegatedRight optimization for riscv: And + Not -> AndNot Or + Not -> OrNot Xor + Not -> XorNot By compiling facebook app using dex2oat I got: 169 cases of And + Not pattern 9 cases of Or + Not pattern 1 case of Xor + Not pattern. Test: art/test/testrunner/testrunner.py --target --64 --ndebug --optimizing Change-Id: Icc2db96770378005d2fb01176298a067e1a0e4ad --- compiler/optimizing/graph_visualizer.cc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'compiler/optimizing/graph_visualizer.cc') diff --git a/compiler/optimizing/graph_visualizer.cc b/compiler/optimizing/graph_visualizer.cc index bc8ebb5917..46db4489d6 100644 --- a/compiler/optimizing/graph_visualizer.cc +++ b/compiler/optimizing/graph_visualizer.cc @@ -628,12 +628,12 @@ class HGraphVisualizerPrinter final : public HGraphDelegateVisitor { DataType::ToSigned(arg_type)); } -#if defined(ART_ENABLE_CODEGEN_arm) || defined(ART_ENABLE_CODEGEN_arm64) - void VisitMultiplyAccumulate(HMultiplyAccumulate* instruction) override { + void VisitBitwiseNegatedRight(HBitwiseNegatedRight* instruction) override { StartAttributeStream("kind") << instruction->GetOpKind(); } - void VisitBitwiseNegatedRight(HBitwiseNegatedRight* instruction) override { +#if defined(ART_ENABLE_CODEGEN_arm) || defined(ART_ENABLE_CODEGEN_arm64) + void VisitMultiplyAccumulate(HMultiplyAccumulate* instruction) override { StartAttributeStream("kind") << instruction->GetOpKind(); } -- cgit v1.2.3-59-g8ed1b