From 077188411c692f82b0785597fee030810a2a5841 Mon Sep 17 00:00:00 2001 From: Artem Serov Date: Mon, 24 Feb 2020 18:51:42 +0000 Subject: ART: Introduce predicated vector instructions. This CL introduces a minimal changes to the IR to support autovectorization with use of predicated execution of SIMD instructions (e.g. Arm SVE). Test: test-art-target, test-art-host. Change-Id: Ibb7c5520fec6b858fb29f0dde19ec65501831a3a --- compiler/optimizing/graph_checker.cc | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'compiler/optimizing/graph_checker.cc') diff --git a/compiler/optimizing/graph_checker.cc b/compiler/optimizing/graph_checker.cc index 95cfe3ebdb..ece88a01b4 100644 --- a/compiler/optimizing/graph_checker.cc +++ b/compiler/optimizing/graph_checker.cc @@ -25,6 +25,7 @@ #include "base/bit_vector-inl.h" #include "base/scoped_arena_allocator.h" #include "base/scoped_arena_containers.h" +#include "code_generator.h" #include "handle.h" #include "mirror/class.h" #include "obj_ptr-inl.h" @@ -1141,4 +1142,26 @@ void GraphChecker::VisitTypeConversion(HTypeConversion* instruction) { } } +void GraphChecker::VisitVecOperation(HVecOperation* instruction) { + VisitInstruction(instruction); + if (codegen_ == nullptr) { + return; + } + + if (!codegen_->SupportsPredicatedSIMD() && instruction->IsPredicated()) { + AddError(StringPrintf( + "%s %d must not be predicated.", + instruction->DebugName(), + instruction->GetId())); + } + + if (codegen_->SupportsPredicatedSIMD() && + (instruction->MustBePredicatedInPredicatedSIMDMode() != instruction->IsPredicated())) { + AddError(StringPrintf( + "%s %d predication mode is incorrect; see HVecOperation::MustBePredicated.", + instruction->DebugName(), + instruction->GetId())); + } +} + } // namespace art -- cgit v1.2.3-59-g8ed1b