From 1ba0f596e9e4ddd778ab431237d11baa85594eba Mon Sep 17 00:00:00 2001 From: Nicolas Geoffray Date: Mon, 27 Oct 2014 15:14:55 +0000 Subject: Support hard float on arm in optimizing compiler. Also bump oat version, needed after latest hard float switch. Change-Id: Idf5acfb36c07e74acff00edab998419a3c6b2965 --- compiler/optimizing/code_generator.cc | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'compiler/optimizing/code_generator.cc') diff --git a/compiler/optimizing/code_generator.cc b/compiler/optimizing/code_generator.cc index c4286a401b..28ff1cf83a 100644 --- a/compiler/optimizing/code_generator.cc +++ b/compiler/optimizing/code_generator.cc @@ -111,6 +111,20 @@ size_t CodeGenerator::FindFreeEntry(bool* array, size_t length) { } } LOG(FATAL) << "Could not find a register in baseline register allocator"; + UNREACHABLE(); + return -1; +} + +size_t CodeGenerator::FindTwoFreeConsecutiveEntries(bool* array, size_t length) { + for (size_t i = 0; i < length - 1; ++i) { + if (!array[i] && !array[i + 1]) { + array[i] = true; + array[i + 1] = true; + return i; + } + } + LOG(FATAL) << "Could not find a register in baseline register allocator"; + UNREACHABLE(); return -1; } @@ -180,6 +194,11 @@ void CodeGenerator::AllocateRegistersLocally(HInstruction* instruction) const { } else if (loc.IsFpuRegister()) { DCHECK(!blocked_fpu_registers_[loc.reg()]); blocked_fpu_registers_[loc.reg()] = true; + } else if (loc.IsFpuRegisterPair()) { + DCHECK(!blocked_fpu_registers_[loc.AsFpuRegisterPairLow()]); + blocked_fpu_registers_[loc.AsFpuRegisterPairLow()] = true; + DCHECK(!blocked_fpu_registers_[loc.AsFpuRegisterPairHigh()]); + blocked_fpu_registers_[loc.AsFpuRegisterPairHigh()] = true; } else if (loc.IsRegisterPair()) { DCHECK(!blocked_core_registers_[loc.AsRegisterPairLow()]); blocked_core_registers_[loc.AsRegisterPairLow()] = true; -- cgit v1.2.3-59-g8ed1b