From b5860fb459f1ed71f39d8a87b45bee6727d79fe8 Mon Sep 17 00:00:00 2001 From: buzbee Date: Sat, 21 Jun 2014 15:31:01 -0700 Subject: Register promotion support for 64-bit targets Not sufficiently tested for 64-bit targets, but should be fairly close. A significant amount of refactoring could stil be done, (in later CLs). With this change we are not making any changes to the vmap scheme. As a result, it is a requirement that if a vreg is promoted to both a 32-bit view and the low half of a 64-bit view it must share the same physical register. We may change this restriction later on to allow for more flexibility for 32-bit Arm. For example, if v4, v5, v4/v5 and v5/v6 are all hot enough to promote, we'd end up with something like: v4 (as an int) -> r10 v4/v5 (as a long) -> r10 v5 (as an int) -> r11 v5/v6 (as a long) -> r11 Fix a couple of ARM64 bugs on the way... Change-Id: I6a152b9c164d9f1a053622266e165428045362f3 --- compiler/dex/quick/gen_common.cc | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'compiler/dex/quick/gen_common.cc') diff --git a/compiler/dex/quick/gen_common.cc b/compiler/dex/quick/gen_common.cc index 2c59055243..fe905623b2 100644 --- a/compiler/dex/quick/gen_common.cc +++ b/compiler/dex/quick/gen_common.cc @@ -1122,6 +1122,9 @@ void Mir2Lir::GenThrow(RegLocation rl_src) { } } +#define IsSameReg(r1, r2) \ + (GetRegInfo(r1)->Master()->GetReg().GetReg() == GetRegInfo(r2)->Master()->GetReg().GetReg()) + // For final classes there are no sub-classes to check and so we can answer the instance-of // question with simple comparisons. void Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, @@ -1132,8 +1135,9 @@ void Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, Re RegLocation object = LoadValue(rl_src, kRefReg); RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); RegStorage result_reg = rl_result.reg; - if (result_reg == object.reg) { + if (IsSameReg(result_reg, object.reg)) { result_reg = AllocTypedTemp(false, kCoreReg); + DCHECK(!IsSameReg(result_reg, object.reg)); } LoadConstant(result_reg, 0); // assume false LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg, 0, NULL); -- cgit v1.2.3-59-g8ed1b