From b01bf15d18f9b08d77e7a3c6e2897af0e02bf8ca Mon Sep 17 00:00:00 2001 From: buzbee Date: Tue, 13 May 2014 15:59:07 -0700 Subject: 64-bit temp register support. Add a 64-bit temp register allocation path. The recent physical register handling rework supports multiple views of the same physical register (or, such as for Arm's float/double regs, different parts of the same physical register). This CL adds a 64-bit core register view for 64-bit targets. In short, each core register will have a 64-bit name, and a 32-bit name. The different views will be kept in separate register pools, but aliasing will be tracked. The core temp register allocation routines will be largely identical - except for 32-bit targets, which will continue to use pairs of 32-bit core registers for holding long values. Change-Id: I8f118e845eac7903ad8b6dcec1952f185023c053 --- compiler/dex/quick/codegen_util.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'compiler/dex/quick/codegen_util.cc') diff --git a/compiler/dex/quick/codegen_util.cc b/compiler/dex/quick/codegen_util.cc index d58015a979..6ccf252a14 100644 --- a/compiler/dex/quick/codegen_util.cc +++ b/compiler/dex/quick/codegen_util.cc @@ -991,7 +991,7 @@ void Mir2Lir::Materialize() { /* Convert LIR into machine code. */ AssembleLIR(); - if (cu_->verbose) { + if ((cu_->enable_debug & (1 << kDebugCodegenDump)) != 0) { CodegenDump(); } } -- cgit v1.2.3-59-g8ed1b