From 55d0eac918321e0525f6e6491f36a80977e0d416 Mon Sep 17 00:00:00 2001 From: Mark Mendell Date: Thu, 6 Feb 2014 11:02:52 -0800 Subject: Support Direct Method/Type access for X86 Thumb generates code to optimize calls to methods within core.oat. Implement this for X86 as well, but take advantage of mov with 32 bit immediate and call relative with 32 bit immediate. Fix some incorrect return locations for long inlines. Change-Id: I1907bdfc7574f3d0aa76c7fad13dc537acdf1ed3 Signed-off-by: Mark Mendell --- compiler/dex/quick/codegen_util.cc | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'compiler/dex/quick/codegen_util.cc') diff --git a/compiler/dex/quick/codegen_util.cc b/compiler/dex/quick/codegen_util.cc index 5e0fed7fd9..05eb360a6b 100644 --- a/compiler/dex/quick/codegen_util.cc +++ b/compiler/dex/quick/codegen_util.cc @@ -1186,4 +1186,37 @@ LIR *Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, int temp_reg, int base_reg, void Mir2Lir::AddSlowPath(LIRSlowPath* slowpath) { slow_paths_.Insert(slowpath); } + +void Mir2Lir::LoadCodeAddress(int dex_method_index, InvokeType type, SpecialTargetRegister symbolic_reg) { + LIR* data_target = ScanLiteralPool(code_literal_list_, dex_method_index, 0); + if (data_target == NULL) { + data_target = AddWordData(&code_literal_list_, dex_method_index); + data_target->operands[1] = type; + } + LIR* load_pc_rel = OpPcRelLoad(TargetReg(symbolic_reg), data_target); + AppendLIR(load_pc_rel); + DCHECK_NE(cu_->instruction_set, kMips) << reinterpret_cast(data_target); +} + +void Mir2Lir::LoadMethodAddress(int dex_method_index, InvokeType type, SpecialTargetRegister symbolic_reg) { + LIR* data_target = ScanLiteralPool(method_literal_list_, dex_method_index, 0); + if (data_target == NULL) { + data_target = AddWordData(&method_literal_list_, dex_method_index); + data_target->operands[1] = type; + } + LIR* load_pc_rel = OpPcRelLoad(TargetReg(symbolic_reg), data_target); + AppendLIR(load_pc_rel); + DCHECK_NE(cu_->instruction_set, kMips) << reinterpret_cast(data_target); +} + +void Mir2Lir::LoadClassType(uint32_t type_idx, SpecialTargetRegister symbolic_reg) { + // Use the literal pool and a PC-relative load from a data word. + LIR* data_target = ScanLiteralPool(class_literal_list_, type_idx, 0); + if (data_target == nullptr) { + data_target = AddWordData(&class_literal_list_, type_idx); + } + LIR* load_pc_rel = OpPcRelLoad(TargetReg(symbolic_reg), data_target); + AppendLIR(load_pc_rel); +} + } // namespace art -- cgit v1.2.3-59-g8ed1b