From 091cc408e9dc87e60fb64c61e186bea568fc3d3a Mon Sep 17 00:00:00 2001 From: buzbee Date: Mon, 31 Mar 2014 10:14:40 -0700 Subject: Quick compiler: allocate doubles as doubles Significant refactoring of register handling to unify usage across all targets & 32/64 backends. Reworked RegStorage encoding to allow expanded use of x86 xmm registers; removed vector registers as a separate register type. Reworked RegisterInfo to describe aliased physical registers. Eliminated quite a bit of target-specific code and generalized common code. Use of RegStorage instead of int for registers now propagated down to the NewLIRx() level. In future CLs, the NewLIRx() routines will be replaced with versions that are explicit about what kind of operand they expect (RegStorage, displacement, etc.). The goal is to eventually use RegStorage all the way to the assembly phase. TBD: MIPS needs verification. TBD: Re-enable liveness tracking. Change-Id: I388c006d5fa9b3ea72db4e37a19ce257f2a15964 --- compiler/dex/quick/codegen_util.cc | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) (limited to 'compiler/dex/quick/codegen_util.cc') diff --git a/compiler/dex/quick/codegen_util.cc b/compiler/dex/quick/codegen_util.cc index 0596d4fff0..396195450a 100644 --- a/compiler/dex/quick/codegen_util.cc +++ b/compiler/dex/quick/codegen_util.cc @@ -254,7 +254,7 @@ void Mir2Lir::DumpPromotionMap() { PromotionMap v_reg_map = promotion_map_[i]; std::string buf; if (v_reg_map.fp_location == kLocPhysReg) { - StringAppendF(&buf, " : s%d", v_reg_map.FpReg & FpRegMask()); + StringAppendF(&buf, " : s%d", RegStorage::RegNum(v_reg_map.FpReg)); } std::string buf3; @@ -942,7 +942,7 @@ Mir2Lir::Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena switch_tables_(arena, 4, kGrowableArraySwitchTables), fill_array_data_(arena, 4, kGrowableArrayFillArrayData), tempreg_info_(arena, 20, kGrowableArrayMisc), - reginfo_map_(arena, 64, kGrowableArrayMisc), + reginfo_map_(arena, RegStorage::kMaxRegs, kGrowableArrayMisc), pointer_storage_(arena, 128, kGrowableArrayMisc), data_offset_(0), total_size_(0), @@ -1185,8 +1185,19 @@ std::vector* Mir2Lir::ReturnCallFrameInformation() { RegLocation Mir2Lir::NarrowRegLoc(RegLocation loc) { loc.wide = false; - if (loc.reg.IsPair()) { - loc.reg = loc.reg.GetLow(); + if (loc.location == kLocPhysReg) { + if (loc.reg.IsPair()) { + loc.reg = loc.reg.GetLow(); + } else { + // FIXME: temp workaround. + // Issue here: how do we narrow to a 32-bit value in 64-bit container? + // Probably the wrong thing to narrow the RegStorage container here. That + // should be a target decision. At the RegLocation level, we're only + // modifying the view of the Dalvik value - this is orthogonal to the storage + // container size. Consider this a temp workaround. + DCHECK(loc.reg.IsDouble()); + loc.reg = loc.reg.DoubleToLowSingle(); + } } return loc; } -- cgit v1.2.3-59-g8ed1b