From b01bf15d18f9b08d77e7a3c6e2897af0e02bf8ca Mon Sep 17 00:00:00 2001 From: buzbee Date: Tue, 13 May 2014 15:59:07 -0700 Subject: 64-bit temp register support. Add a 64-bit temp register allocation path. The recent physical register handling rework supports multiple views of the same physical register (or, such as for Arm's float/double regs, different parts of the same physical register). This CL adds a 64-bit core register view for 64-bit targets. In short, each core register will have a 64-bit name, and a 32-bit name. The different views will be kept in separate register pools, but aliasing will be tracked. The core temp register allocation routines will be largely identical - except for 32-bit targets, which will continue to use pairs of 32-bit core registers for holding long values. Change-Id: I8f118e845eac7903ad8b6dcec1952f185023c053 --- compiler/dex/frontend.cc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'compiler/dex/frontend.cc') diff --git a/compiler/dex/frontend.cc b/compiler/dex/frontend.cc index 3bc060ba27..77b5057538 100644 --- a/compiler/dex/frontend.cc +++ b/compiler/dex/frontend.cc @@ -75,6 +75,7 @@ static uint32_t kCompilerDebugFlags = 0 | // Enable debug/testing modes // (1 << kDebugShowSummaryMemoryUsage) | // (1 << kDebugShowFilterStats) | // (1 << kDebugTimings) | + // (1 << kDebugCodegenDump) | 0; CompilationUnit::CompilationUnit(ArenaPool* pool) @@ -852,6 +853,10 @@ static CompiledMethod* CompileMethod(CompilerDriver& driver, } } + if (cu.verbose) { + cu.enable_debug |= (1 << kDebugCodegenDump); + } + /* * TODO: rework handling of optimization and debug flags. Should we split out * MIR and backend flags? Need command-line setting as well. @@ -877,6 +882,7 @@ static CompiledMethod* CompileMethod(CompilerDriver& driver, if (cu.instruction_set == kArm64) { // TODO(Arm64): enable optimizations once backend is mature enough. cu.disable_opt = ~(uint32_t)0; + cu.enable_debug |= (1 << kDebugCodegenDump); } cu.StartTimingSplit("BuildMIRGraph"); -- cgit v1.2.3-59-g8ed1b