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2014-04-25ART: Enables x86_64 disassembly Vladimir Kostyukov
This patch (a) cuts a REX prefix from the instruction and (b) adds missed 32bit disp to instructions with ModR/M and SIB bytes. Change-Id: I2674678224ca27746b33d4006ed38d497972309f Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
2014-04-24Merge "ART: Fixes an issue with REX prefix for instructions with no ModRM byte" Ian Rogers
2014-04-17ART: Fixes an issue with REX prefix for instructions with no ModRM byte Vladimir Kostyukov
There are instructions (such as push, pop, mov) in the x86 ISA that encode first operands in their opcodes (opcode + reg). In order to enable an extended 64bit registers (R9-R15) a special prefix REX.B should be emitted before such instructions. This patch fixes the issue when REX.R prefix was emitted before instructions with no MorRM byte. So, the REX-prefix was simply ignored by CPU for those instructions whose operands are encoded in their opcodes. This patch makes the jni_compiler_test passed with JNI compiler enabled for x86_64 target. Change-Id: Ib84da1cf9f8ff96bd7afd4e0fc53078f3231f8ec Signed-off-by: Vladimir Kostyukov <vladimir.kostyukov@intel.com>
2014-04-16Preparation for transition to libc++. Ian Rogers
Move the dependency on libc++ to its own makefile so that we can switch in a single place between libc++ and stlport. Change-Id: Ie61e7d054dcd049e36d5e7298c27d8a4abe6edf7
2014-04-09Revert "Revert "Revert "Use trampolines for calls to helpers""" Dave Allison
This reverts commit f9487c039efb4112616d438593a2ab02792e0304. Change-Id: Id48a4aae4ecce73db468587967968a3f7618b700
2014-04-09Revert "Revert "Use trampolines for calls to helpers"" Dave Allison
This reverts commit 081f73e888b3c246cf7635db37b7f1105cf1a2ff. Change-Id: Ibd777f8ce73cf8ed6c4cb81d50bf6437ac28cb61 Conflicts: compiler/dex/quick/mir_to_lir.h
2014-04-07Revert "Use trampolines for calls to helpers" Dave Allison
This reverts commit 754ddad084ccb610d0cf486f6131bdc69bae5bc6. Change-Id: Icd979adee1d8d781b40a5e75daf3719444cb72e8
2014-04-04Use trampolines for calls to helpers Dave Allison
This is an ARM specific optimization to the compiler that uses trampoline islands to make calls to runtime helper functions. The intention is to reduce the size of the generated code (by 2 bytes per call) without affecting performance. By default this is on when generating an OAT file. It is off when compiling to memory. To switch this off in dex2oat, use the command line option: --no-helper-trampolines Enhances disassembler to print the trampoline entry on the BL instruction like this: 0xb6a850c0: f7ffff9e bl -196 (0xb6a85000) ; pTestSuspend Bug: 12607709 Change-Id: I9202bdb7cf21252ad807bd48701f1f6ce8e3d0fe
2014-04-03Disassemble Thumb2 shifts and more VFP instructions. Vladimir Marko
Disassemble Thumb2 instructions LSL, LSR, ASR, ROR and VFP instructions VABS, VADD, VSUB, VMOV, VMUL, VNMUL, VDIV. Clean up disassembly of VCMP, VCMPE, VNEG and VSQRT. These could have been erroneously used for other insns (VSQRT for VMOV was encountered) and one VSQRT branch was unreachable. Remove duplicate VMOV opcodes from compiler. Change-Id: I160a1e3e4b6eabb6a5101ce348ffd49c0573257d
2014-04-01Allow mixing of thread offsets between 32 and 64bit architectures. Ian Rogers
Begin a more full implementation x86-64 REX prefixes. Doesn't implement 64bit thread offset support for the JNI compiler. Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
2014-03-26Relaxed memory barriers for x86 Razvan A Lupusoru
X86 provides stronger memory guarantees and thus the memory barriers can be optimized. This patch ensures that all memory barriers for x86 are treated as scheduling barriers. And in cases where a barrier is needed (StoreLoad case), an mfence is used. Change-Id: I13d02bf3f152083ba9f358052aedb583b0d48640 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
2014-03-25Fix imm5 and shift_type detection Dmitriy Ivanov
Bug: 13628315 Change-Id: I8ff044cc18721b7ea50c75c796a2fb63a1e189f9
2014-03-14x86-64 disassembler support. Ian Rogers
Change-Id: I0ae39ae1ffdae2500ff368354f9e4702445176f0
2014-03-13Avoid bus error from reading unaligned 64-bit literal Brian Carlstrom
Change-Id: I5932f130e6a8d31e09ef615e8544ff0e1073ede9
2014-03-10Merge "AArch64: Add ARM64 Disassembler" Ian Rogers
2014-03-10AArch64: Add ARM64 Disassembler Serban Constantinescu
This patch adds disassembler support for ARM64 based on VIXL. Change-Id: Ic7f5e197350809632145d932dbae8f6c16aebd13 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
2014-03-10ARM: Remove duplicated instructions; add vcvt, vmla, vmls disassembler. Zheng Xu
Remove kThumb2VcvtID in the assembler which was duplicated. Add vcvt, vmla, vmls in the disassembler. Change-Id: I14cc39375c922c9917274d8dcfcb515e888fdf26
2014-02-28Fix clang to compile and run host tests. Ian Rogers
Don't use the computed goto interpreter with clang 3.4 as it causes compilation to hang. Avoid inclusion of LLVM_(HOST|DEVICE)_BUILD_MK except for with portable as it sets clang incompatible cflags. Most fixes are self-evident, for the quick dex file method inliner the enums were being used with ostreams, so fix the enums and operator out python script to allow this. Note this change effects portable but this is untestable as portable was broken by ELF file and mc linker changes. Change-Id: Ia54348f6b1bd3f76d3b71c6e8c5f97626386b903
2014-02-20Inline x86 String.indexOf Mark Mendell
Take advantage of the presence of a constant search char or start index to tune the generated code. Change-Id: I0adcf184fb91b899a95aa4d8ef044a14deb51d88 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2014-02-18art: convert makefiles to support multilib build Colin Cross
Convert makefiles to allow for building two architectures at the same time. More changes may be necessary to get the tests to build. Change-Id: I02ba11706b7e5b5592d76e43c167bcbf0e665b93
2014-02-11Support to generate inline long to FP bytecodes for x86 Razvan A Lupusoru
long-to-float and long-to-double are now generated inline instead of calling a helper routine. The conversion is done by using x87. Change-Id: I196e526afec1be212898baceca8527549c3655b6 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
2014-02-06Object model changes to support 64bit. Ian Rogers
Modify mirror objects so that references between them use an ObjectReference value type rather than an Object* so that functionality to compress larger references can be captured in the ObjectRefererence implementation. ObjectReferences are 32bit and all other aspects of object layout remain as they are currently. Expand fields in objects holding pointers so they can hold 64bit pointers. Its expected the size of these will come down by improving where we hold compiler meta-data. Stub out x86_64 architecture specific runtime implementation. Modify OutputStream so that reads and writes are of unsigned quantities. Make the use of portable or quick code more explicit. Templatize AtomicInteger to support more than just int32_t as a type. Add missing, and fix issues relating to, missing annotalysis information on the mutator lock. Refactor and share implementations for array copy between System and uses elsewhere in the runtime. Fix numerous 64bit build issues. Change-Id: I1a5694c251a42c9eff71084dfdd4b51fff716822
2014-02-05Specializing x86 range argument copying Razvan A Lupusoru
The ARM implementation of range argument copying was specialized in some cases. For all other architectures, it would fall back to generating memcpy. This patch updates the x86 implementation so it does not call memcpy and instead generates loads and stores, favoring movement of 128-bit chunks. Change-Id: Ic891e5609a4b0e81a47c29cc5a9b301bd10a1933 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
2014-01-28Merge "Improve x86 long multiply and shifts" Ian Rogers
2014-01-24Reduce x86 sequence for GP pair to XMM Razvan A Lupusoru
Added support for punpckldq which is useful for interleaving 32-bit values from two xmm registers. This new instruction is now used for transfers from GP pairs to XMM in order to reduce path length. Change-Id: I70d9b69449dfcfb9a94a628deb74a7cffe96bac7 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
2014-01-24Improve x86 long multiply and shifts Mark Mendell
Generate inline code for long shifts by constants and do long multiplication inline. Convert multiplication by a constant to a shift when we can. Fix some x86 assembler problems and add the new instructions that were needed (64 bit shifts). Change-Id: I6237a31c36159096e399d40d01eb6bfa22ac2772 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2014-01-24Improve x86 long divide Mark Mendell
Implement inline division for literal and variable divisors. Use the general case for dividing by a literal by using a double length multiply by the appropriate constant with fixups. This is the Hacker's Delight algorithm. Change-Id: I563c250f99d89fca5ff8bcbf13de74de13815cfe Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2014-01-08Merge "Add conditional move support to x86 and allow GenMinMax to use it" Ian Rogers
2014-01-08Inline codegen for long-to-double on ARM. Ian Rogers
Change-Id: I4fc443c1b942a2231d680fc2c7a1530c86104584
2014-01-08Add conditional move support to x86 and allow GenMinMax to use it Razvan A Lupusoru
X86 supports conditional moves which is useful for reducing branchiness. This patch adds support to the x86 backend to generate conditional reg to reg operations. Both encoder and decoder support was added for cmov. The x86 version of GenMinMax used for generating inlined version Math.min/max has been updated to make use of the conditional move support. Change-Id: I92c5428e40aa8ff88bd3071619957ac3130efae7 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
2013-12-20Tidy up memory barriers. Ian Rogers
Change-Id: I937ea93e6df1835ecfe2d4bb7d84c24fe7fc097b
2013-12-12Disassemble more x86 instructions Mark Mendell
By using oatdump on the core.oat, I found a couple more instructions that didn't disassemble properly. These included another form of imul and some FP instructions used by the JNI code. Now the only unknown opcodes I could find seem to be literal data at the end of the method. Change-Id: Icea1da1c7d1f9dce99e6b6517cfca34b47d6827a Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2013-12-11Add missing x86 imul opcode to disassembler Mark Mendell
When playing with ART, I noticed that an integer multiply didn't disassemble properly. This patch adds the instruction. Change-Id: Ic4d4921b1b301a9d674a257f094e8b3d834ed991 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2013-12-03Unsafe.compareAndSwapLong() intrinsic for x86. Vladimir Marko
Change-Id: Idbc5371a62dfdd84485a657d4548990519200205
2013-11-26Intrinsic Unsafe.CompareAndSwapLong() for ARM. Vladimir Marko
(cherry picked from cb53fcd79b1a5ce608208ec454b5c19f64aaba37) Change-Id: Iadd3cc8b4ed390670463b80f8efd579ce6ece226
2013-11-19Clean up kOpCmp on ARM. Vladimir Marko
kThumb2CmnRI8M is now used. Change-Id: I300299258ed99d86c300dee45c904c360dd44638
2013-11-15Fix Thumb2 ldrd/strd disassembly. Vladimir Marko
Change-Id: Ie75aeab5b970640e90e567621ac45ce1a3a7c377
2013-11-07Disassemble Thumb2 vstm/vldm/vstr/vldr/vpush/vpop/vmov/vmrs. Vladimir Marko
Not all versions of vmov are disassembled. Change-Id: I876199f7536d2a9429106deab821016fe8972469
2013-11-05Support hardware divide instruction Dave Allison
Bug: 11299025 Uses sdiv for division and a combo of sdiv, mul and sub for modulus. Only does this on processors that are capable of the sdiv instruction, as determined by the build system. Also provides a command line arg --instruction-set-features= to allow cross compilation. Makefile adds the --instruction-set-features= arg to build-time dex2oat runs and defaults it to something obtained from the target architecture. Provides a GetInstructionSetFeatures() function on CompilerDriver that can be queried for various features. The only feature supported right now is hasDivideInstruction(). Also adds a few more instructions to the ARM disassembler b/11535253 is an addition to this CL to be done later. Change-Id: Ia8aaf801fd94bc71e476902749cf20f74eba9f68
2013-10-28Fix whitespace-sensitive build. Vladimir Marko
Change-Id: I82c6c49e253275543831dbaf288cb63d759ea20a
2013-10-28Add byte swap instructions for ARM and x86. Vladimir Marko
Change-Id: I03fdd61ffc811ae521141f532b3e04dda566c77d
2013-10-04Implement thumb expansion of immediates. Ian Rogers
Change-Id: Ie50c17f82cbf97a16b58350b378914030cc0499f
2013-09-09Move disassembler out of runtime. Ian Rogers
Bug: 9877500. Change-Id: Ica6d9f5ecfd20c86e5230a2213827bd78cd29a29
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