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2015-04-29Fix for incorrect encode and parse of PEXTRW instruction nikolay serdjuk
The instruction PEXTRW encoded by sequence 66 0F 3A 15 was incorrectly encoded in compiler table and incorrectly parsed by disassembler. Change-Id: Ib4d4db923cb15a76e74f13f6b5514cb0d1cbe164 Signed-off-by: nikolay serdjuk <nikolay.y.serdjuk@intel.com>
2015-04-22Replace NULL with nullptr Mathieu Chartier
Also fixed some lines that were too long, and a few other minor details. Change-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb
2015-04-09Merge "[MIPS] Refactoring code for disassembler" Andreas Gampe
2015-04-09Merge "Fix for incorrect parse of PEXTRW instruction" Andreas Gampe
2015-04-09[MIPS] Refactoring code for disassembler Goran Jakovljevic
Code for mips64 is merged with code for mips. Change-Id: I2e3f2118c69a189787ae8e7f09adb4ee5c0d00d9
2015-04-07Merge "Fix address formatting in Mips64 disassembler." David Srbecky
2015-04-07Merge "Build 32-bit version of the disassembler as well." David Srbecky
2015-04-07Fix for incorrect parse of PEXTRW instruction nikolay serdjuk
The instruction PEXTRW encoded by sequence 66 0F C5 has form: PEXTRW reg, xmm, imm8. Its reg is encoded in the REG part and xmm is encoded in the R/M part of ModR/M byte. Since the order is opposite to the PEXTRB and PEXTRD, we have to set 'load' to true and 'store' leave as false. Change-Id: I32c42ea005eec29f7bf969f275c36ffa0a95fa6d
2015-04-06ART: Enable more Clang warnings Andreas Gampe
Change-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c
2015-04-06Fix address formatting in Mips64 disassembler. David Srbecky
Use FormatInstructionPointer like all the other disassemblers. This ensures that the 'absolute_addresses' option is honoured. Change-Id: I5580319cc4fad40e00f3fbbde25b142f7c689390
2015-04-06Build 32-bit version of the disassembler as well. David Srbecky
Change-Id: I22ecc2611c3b05b1031b42abdb5bf8c245220e03
2015-04-02Merge "[optimizing] Implement x86/x86_64 math intrinsics" Andreas Gampe
2015-04-01[optimizing] Implement x86/x86_64 math intrinsics Mark Mendell
Implement floor/ceil/round/RoundFloat on x86 and x86_64. Implement RoundDouble on x86_64. Add support for roundss and roundsd on both architectures. Support them in the disassembler as well. Add the instruction set features for x86, as the 'round' instruction is only supported if SSE4.1 is supported. Fix the tests to handle the addition of passing the instruction set features to x86 and x86_64. Add assembler tests for roundsd and roundss to x86_64 assembler tests. Change-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-03-31ARM64: Update to VIXL 1.9. Serban Constantinescu
Update VIXL's interface to VIXL 1.9. Change-Id: Iebae947539cbad65488b7195aaf01de284b71cbb Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
2015-03-20ART: Add Mips32r6 backend support Douglas Leung
Add Mips32r6 compiler support. Don't use deprecated Mips32r2 instructions if running in Mips32r6 mode. Change-Id: I54e689aa8c026ccb75c4af515aa2794f471c9f67
2015-03-06Initial support for quick compiler on MIPS64r6. Maja Gagic
Change-Id: I6f43027b84e4a98ea320cddb972d9cf39bf7c4f8
2015-03-06ART: Enable the use of relative addresses in the arm64 disassembler. Alexandre Rames
Also, only keep register aliases for the link register 'lr' and the thread register 'tr' in the arm64 disassembler. Other aliases are not very important, and this way we don't have to provide aliases specialised for Quick or Optimizing. Change-Id: Ie7a04910f0c587710a0cf2648203d7e89eab5d1f
2015-02-28ART: Fix Mips disassembler for some floating point instructions. Douglas Leung
Change-Id: I2b661a8dae4cd924c081df85f570007cf645769c
2015-02-03ARM/ARM64: Dump thread offset. Zheng Xu
Dump thread offset in compiler verbose log for arm32/arm64 and oatdump for arm64. Before patch : 0x4e: ldr lr, [rSELF, #604] After patch : 0x4e: ldr lr, [rSELF, #604] ; pTestSuspend Change-Id: I514e69dc44b1cf4c8a8fa085b31f93cf6a1b7c91
2015-02-02Merge "ART: Fix x86 disassembler" Andreas Gampe
2015-01-30Add options for building/testing with coverage. Dan Albert
acov --clean mm -B NATIVE_COVERAGE=true ART_COVERAGE=true test-art-host acov --host -B is needed because you need to be sure you rebuild *all* of ART with coverage. Change-Id: Ib94ef610bd1b44dc45624877710ed733051b7a50
2015-01-29Remove libcxx.mk cruft. Dan Albert
This is on by default now. No need to leave it in the makefiles. Change-Id: I20eab7426da4bbbf8b70ffc5b9af7b97487d885d
2015-01-27ART: Fix x86 disassembler Andreas Gampe
Index 4 in SIB is valid when given Rex.x, where it denotes r12 and not the invalid rsp. Bug: 19149560 Change-Id: I1a74bcbb1ccf3686e45a3df5d852a86444f9d850
2015-01-15ART: Allow to compile interpret-only mips64 files Andreas Gampe
Include enough infrastructure to allow cross-compiling for mips64, interpret-only. This includes the instruction-set-features, frame size info and utils assembler. Also add a disassembler for oatdump, and support in patchoat. Note: the runtime cannot run mips64, yet. Change-Id: Id106581fa76b478984741c62a8a03be0f370d992
2015-01-13ART: Use jalr instead of jr for Mips Andreas Gampe
Use the jalr instruction instead of jr in stubs and compiled code. Change-Id: Idacc5167a5bb0113dc2e7716e4767e5ed07b5e0b
2015-01-06Improve Thumb disassembler for LDR/STR/PUSH/POP/BKPT. Vladimir Marko
Disassemble 16-bit Thumb PUSH, POP, BKPT. Clean up 32-bit load/store to handle all cases (including previously unrecognized indexed load/store) in one place; this also fixes LDRSH erroneously disassembled as LDRSB. Recognize more UNDEFINED instructions and other minor cleanup. Change-Id: Ifdd177745b70e3f774cc0469deb81191b035f51b
2014-12-16Fix crash in x86 disassembler. Nicolas Geoffray
Probably a typo from last refactoring. Change-Id: I086a87120ca0f0dfddbe803573b0e0f79cc6d945
2014-12-15ART: Do not inline elf writer debug symbols Andreas Gampe
Using Clang, this pushes the frame size of the caller across our limit. Thus forbid inlining. The function is only called once per compile, impact is insignificant. Bug: 18738594 Change-Id: I19c3f1168a5104ab508a8dbf9f2a8c035cb97e3c
2014-12-15ART: Break up x86 disassembler main function Andreas Gampe
The function leads to large stack frames with Clang. Break out some parts and use four char* variables for opcode. Bug: 18733806 Change-Id: I8bf6da6c763175d7081c4231fa5d3b6809316220
2014-12-11ARM: Combine multiply accumulate operations. Ningsheng Jian
Try to combine integer multiply and add(sub) into a MAC operation. For AArch64, also try to combine long type multiply and add(sub). Change-Id: Ic85812e941eb5a66abc355cab81a4dd16de1b66e
2014-11-28Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug. Serban Constantinescu
This patch updates the interface to VIXL 1.7 and enables the debug version of VIXL when ART is built in debug mode. Change-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
2014-11-19Merge "Improvements to the ARM64 disassembler." Ian Rogers
2014-11-17Revert "Arm64: Use the debug version of VIXL for debug builds." Nicolas Geoffray
This reverts commit 195c576fbff290d4c313b67ed24ca36f2531acc4. Change-Id: Id992a43ae346bb4c38a6c47639b02aea838d974a
2014-11-14Arm64: Use the debug version of VIXL for debug builds. Serban Constantinescu
This patch builds the debug version of ART against VIXL debug. In this way VIXL will assert misuses of the assembler and disassembler. Change-Id: Ic4654eb20e420f23b40e96a69be452dc50770c1c Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
2014-11-13Instruction set features for ARM64, MIPS and X86. Ian Rogers
Also, refactor how feature strings are handled so they are additive or subtractive. Make MIPS have features for FPU 32-bit and MIPS v2. Use in the quick compiler rather than #ifdefs that wouldn't have worked in cross-compilation. Add SIMD features for x86/x86-64 proposed in: https://android-review.googlesource.com/#/c/112370/ Bug: 18056890 Change-Id: Ic88ff84a714926bd277beb74a430c5c7d5ed7666
2014-11-07Tidy x86 disassembler Ian Rogers
Change-Id: I2f0a2851a15f5a099a5bc0249e3ea0616cdcd94e
2014-11-04ART: More warnings Andreas Gampe
Enable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general, and -Wunused-but-set-parameter for GCC builds. Change-Id: I81bbdd762213444673c65d85edae594a523836e5
2014-10-30Tidy and reduce ART library dependencies on the host. Ian Rogers
Move to shared rather than static libraries. Avoids capture of all static libraries library dependencies. Change-Id: I2be96e92dad4ed1842d76b044745f2a2e15372eb
2014-10-29Improvements to the ARM64 disassembler. Alexandre Rames
This contains three changes: - Use register aliases in the disassembly. - When loading from a literal pool, show what is being loaded. - Disassemble using absolute addresses on ARM64. This ensures that addresses disassembled are coherent with instruction location addresses shown. Examples of disassembled instructions before and after the changes: Before: movz w17, #0x471f ldr d9, pc+736 (addr 0x72690d50) After: movz wip1, #0x471f ldr d9, pc+736 (addr 0x72690d50) (-745.133) Change-Id: I72fdc160fac26f74126921834f17a581c26fd5d8
2014-10-24Tidy logging code not using UNIMPLEMENTED. Ian Rogers
Change-Id: I7a79c1671a6ff8b2040887133b3e0925ef9a3cfe
2014-10-22C++11 related clean-up of DISALLOW_.. Ian Rogers
Move DISALLOW_COPY_AND_ASSIGN to delete functions. By no having declarations with no definitions this prompts better warning messages so deal with these by correcting the code. Add a DISALLOW_ALLOCATION and use for ValueObject and mirror::Object. Make X86 assembly operand types ValueObjects to fix compilation errors. Tidy the use of iostream and ostream. Avoid making cutils a dependency via mutex-inl.h for tests that link against libart. Push tracing dependencies into appropriate files and mutex.cc. x86 32-bit host symbols size is increased for libarttest, avoid copying this in run-test 115 by using symlinks and remove this test's higher than normal ulimit. Fix the RunningOnValgrind test in RosAllocSpace to not use GetHeap as it returns NULL when the heap is under construction by Runtime. Change-Id: Ia246f7ac0c11f73072b30d70566a196e9b78472b
2014-10-22Tidy up logging. Ian Rogers
Move gVerboseMethods to CompilerOptions. Now "--verbose-methods=" option to dex2oat rather than runtime argument "-verbose-methods:". Move ToStr and Dumpable out of logging.h, move LogMessageData into logging.cc except for a forward declaration. Remove ConstDumpable as Dump methods are all const (and make this so if not currently true). Make LogSeverity an enum and improve compile time assertions and type checking. Remove log_severity.h that's only used in logging.h. With system headers gone from logging.h, go add to .cc files missing system header includes. Also, make operator new in ValueObject private for compile time instantiation checking. Change-Id: I3228f614500ccc9b14b49c72b9821c8b0db3d641
2014-10-16Make ART compile with GCC -O0 again. Ian Rogers
Tidy up InstructionSetFeatures so that it has a type hierarchy dependent on architecture. Add to instruction_set_test to warn when InstructionSetFeatures don't agree with ones from system properties, AT_HWCAP and /proc/cpuinfo. Clean-up class linker entry point logic to not return entry points but to test whether the passed code is the particular entrypoint. This works around image trampolines that replicate entrypoints. Bug: 17993736 Change-Id: I5f4b49e88c3b02a79f9bee04f83395146ed7be23
2014-10-13ART: ARM64: Fix instruction addresses in the disassembly. Alexandre Rames
Change-Id: Ic8b6e0d5cd15e029de9bc82e0a4fc2e33d07936c
2014-10-09Enable -Wimplicit-fallthrough. Ian Rogers
Falling through switch cases on a clang build must now annotate the fallthrough with the FALLTHROUGH_INTENDED macro. Bug: 17731372 Change-Id: I836451cd5f96b01d1ababdbf9eef677fe8fa8324
2014-09-29ART: Fix some -Wpedantic errors Andreas Gampe
Remove extra semicolons. Dollar signs in C++ identifiers are an extension. Named variadic macros are an extension. Binary literals are a C++14 feature. Enum re-declarations are not allowed. Overflow. Change-Id: I7d16b2217b2ef2959ca69de84eaecc754517714a
2014-09-16Avoid printing absolute addresses in oatdump Brian Carlstrom
- Added printing of OatClass offsets. - Added printing of OatMethod offsets. - Added bounds checks for code size size, code size, mapping table, gc map, vmap table. - Added sanity check of 100k for code size. - Added partial disassembly of questionable code. - Added --no-disassemble to disable disassembly. - Added --no-dump:vmap to disable vmap dumping. - Reordered OatMethod info to be in file order. Bug: 15567083 (cherry picked from commit 34fa79ece5b3a1940d412cd94dbdcc4225aae72f) Change-Id: I2c368f3b81af53b735149a866f3e491c9ac33fb8
2014-09-03ART: Vectorization opcode implementation fixes Lupusoru, Razvan A
This patch fixes the implementation of the x86 vectorization opcodes. Change-Id: I0028d54a9fa6edce791b7e3a053002d076798748 Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com> Signed-off-by: Udayan Banerji <udayan.banerji@intel.com> Signed-off-by: Philbert Lin <philbert.lin@intel.com>
2014-08-26ART: Add non-temporal store support Jean Christophe Beyler
Added non-temporal store support as a hint from the ME. Added the implementation of the memory barrier extended instruction that supports non-temporal stores by explicitly serializing all previous store-to-memory instructions. Change-Id: I8205a92083f9725253d8ce893671a133a0b6849d Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com> Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
2014-08-14Implement inlined shift long for 32bit Yixin Shou
Added support for x86 inlined shift long for 32bit Change-Id: I6caef60dd7d80227c3057fd6f64b0ecb11025afa Signed-off-by: Yixin Shou <yixin.shou@intel.com>
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