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2016-03-21MIPS32: Implement UnsafeCASInt and UnsafeCASObject intrinsics. Alexey Frunze
Change-Id: Ie871763b9a36075fd3d70ee6e2e241ae1ccc36cf
2016-03-10ART: Do not use vixld - workaround to fix dex2oatds. Vladimir Marko
This is a quick workaround for ODR violations caused by linking libvixl.a compiled without VIXL_DEBUG with the libartd-compiler.a compiled with VIXL_DEBUG. Bug: 27588884 Change-Id: Ib1af165f177f125f03cdd99777dff4c2912f6405
2016-02-10MIPS32: peek*/poke*, and String.charAt intrinsics. Chris Larsen
- byte libcore.io.Memory.peekByte(long address) - short libcore.io.Memory.peekShort(long address) - int libcore.io.Memory.peekInt(long address) - long libcore.io.Memory.peekLong(long address) - void libcore.io.Memory.pokeByte(long address, byte value) - void libcore.io.Memory.pokeShort(long address, short value) - void libcore.io.Memory.pokeInt(long address, int value) - void libcore.io.Memory.pokeLong(long address, long value) - char java.lang.String.charAt(int index) Change-Id: I5ff30b61d87313d00f0fd3f0ee09f1c454f9c9fa
2016-02-10ART/Thumb2: Disassemble SBFX/UBFX. Vladimir Marko
Change-Id: I856206de81f41959f68de0653db021903dd1a210
2016-01-20Implemented BitCount as an intrinsic. With unit test. Aart Bik
Rationale: Recognizing this important operation as an intrinsic has various advantages: (1) having the no-side-effects/no-throw allows for much more GVN/LICM/BCE. (2) Some architectures, like x86_64, provide direct support for this operation. Performance improvements on X86_64: CheckersEvalBench (32-bit bitboard): 27,210KNS -> 36,798KNS = + 35% ReversiEvalBench (64-bit bitboard): 52,562KNS -> 89,086KNS = + 69% Change-Id: I65d549b0469b7909b12c6611cdc34a8640a5751f
2016-01-04MIPS: Implement HRor Alexey Frunze
This also fixes differentiation between the SRL and ROTR instructions in the disassembler. Change-Id: Ie19697f8d6ea8fa4e338adde3e3cf8e4a0383eae
2015-12-16MIPS32: improvements in code generation (mostly 64-bit ALU ops) Alexey Frunze
Specifically: - Use the delay slot in InvokeRuntime() for direct entry points - Use kNoOutputOverlap wherever possible - Improve and/or/xor/add/sub with 64-bit integer constants - Improve 64-bit shifts by a constant amount on R2+ - More efficient load/store of 64-bit constants (especially, 0 & +0.0) Change-Id: I86d2217c8b5b8e2a9371effc2ce38b9eec62782b
2015-12-15MIPS32: Fuse long and FP compare & condition in Optimizing. Alexey Frunze
This also does a minor clean-up in the assembler and its test. Bug: 25559148 Change-Id: I9bad3c500b592a09013b56745f70752eb284a842
2015-11-30MIPS32: int java.lang.*.numberOfLeadingZeros Chris Larsen
- int java.lang.Integer.numberOfLeadingZeros(int) - int java.lang.Long.numberOfLeadingZeros(long) Change-Id: Icaf746cb807863f944ff4ebb5da6e6b2846eac58
2015-10-19MIPS64: Disassembler support for rotate instructions. Chris Larsen
Also, tighten the tests for recognizing the various shift commands. The tests, previously, would be unable to distinguish between "shift right logical" and "rotate right" commands. In particular: - SRLV vs. ROTRV - DSRLV vs. DROTRV, - DSRL vs. DROTR, and - DSRL32 vs. DROTR32 Change-Id: I7a6df8ab0d76fd3d34b1207da9915369ad84fa97
2015-10-06MIPS: Assemblers changes needed for optimizing compiler Goran Jakovljevic
Also add assembler tests for MIPS32. Change-Id: I3ab1fba7f3b06eb3b5058861946d675494a30775
2015-09-16Merge "Additional MIPS64 instructions needed by intrinsics code." Andreas Gampe
2015-09-15Add X86 bsf and rotate instructions Mark Mendell
These are for use in new intrinsics. Bsf (Bit Scan Forward) is used in {Long,Integer}NumberOfTrailingZeros and the rotates are used in {Long,Integer}Rotate{Left,Right}. Change-Id: Icb599d7e1eec4e4ea9e5b4f0b1654c7b8d4de678 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-09-10Additional MIPS64 instructions needed by intrinsics code. Chris Larsen
Change-Id: If2a48300aac7a10dadf485d1765fb5bdeed975fe
2015-08-17ART: Some header cleaning around bit-utils Andreas Gampe
Try to remove dependencies where they are not necessary. Change-Id: I5ff35cb17aea369bed3725b1610b50d7eb05b81e
2015-08-14Add 'bsr' instruction to x86 and x86_64 Mark Mendell
Add support for 'bsr' instruction. Add tests. Change-Id: I1cd8b30d7f3f5ee7fbeef8124cc6a31bf8ce59d5 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-08-14Add rep movsw to x86 and x86_64 instructions. Mark Mendell
Add 'REP MOVSW' as a supported instruction for x86 32 and 64 bit. Added tests. Change-Id: I1c615ac1e7fa46c48983c90f791b92be0375c8b8 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-08-12Remove unnecessary `explicit` qualifiers on constructors. Roland Levillain
Change-Id: Id12e392ad50f66a6e2251a68662b7959315dc567
2015-08-06Introduce arch-specific checker tests. Alexandre Rames
- The '.cfg' output is now created on target. - Arch-specific checker tests can be created by inserting a suffix. For example: /// CHECK-START-ARM64: int Main.foo(int) register (after) /// CHECK-DAG: <<Arg:i\d+>> ParameterValue Change-Id: I55cdb37f8e806c7ffdde6b676c8f44ac30b59051
2015-08-04ARM/ARM64: Implement numberOfLeadingZeros intrinsic. Scott Wakeling
Change-Id: I4042fb7a0b75140475dcfca23e8f79d310f5333b
2015-07-30Added disassembler support for repe_cmpsw instruction in x86, x86_64 agicsaki
Also included support for repe_cmpsl instruction. This is a follow up to commit 71311f868e2 which added support for repe_cmpsw in the x86 and x86_64 assemblers. Change-Id: I2beac05a57341539acf96cdf77062facd031a864
2015-06-22Opt compiler: Add disassembly to the '.cfg' output. Alexandre Rames
This is automatically added to the '.cfg' output when using the usual `--dump-cfg` option. Change-Id: I864bfc3a8299c042e72e451cc7730ad8271e4deb
2015-06-19MIPS: Initial version of optimizing compiler for MIPS64R6. Alexey Frunze
Bug: 21555893 Change-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf Signed-off-by: Alexey Frunze <Alexey.Frunze@imgtec.com> Signed-off-by: Douglas Leung <douglas.leung@imgtec.com>
2015-06-04If heap poisoning is on, pass the relevant flag to LOCAL_ASFLAGS. Roland Levillain
This change ensures assembly files honoring heap poisoning (notably used by stub_test) are compiled with -DART_HEAP_POISONING=1 when this feature is turned on. Bug: 21621105 Change-Id: I13fe456cd2733a09bdfd3a9808cfd70513b14698
2015-05-22ARM64: Move xSELF from x18 to x19. Serban Constantinescu
This patch moves xSELF to callee saved x19 and removes support for ETR (external thread register), previously used across native calls. Change-Id: Icee07fbb9292425947f7de33d10a0ddf98c7899b Signed-off-by: Serban Constantinescu <serban.constantinescu@linaro.org>
2015-04-29Fix for incorrect encode and parse of PEXTRW instruction nikolay serdjuk
The instruction PEXTRW encoded by sequence 66 0F 3A 15 was incorrectly encoded in compiler table and incorrectly parsed by disassembler. Change-Id: Ib4d4db923cb15a76e74f13f6b5514cb0d1cbe164 Signed-off-by: nikolay serdjuk <nikolay.y.serdjuk@intel.com>
2015-04-22Replace NULL with nullptr Mathieu Chartier
Also fixed some lines that were too long, and a few other minor details. Change-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb
2015-04-09Merge "[MIPS] Refactoring code for disassembler" Andreas Gampe
2015-04-09Merge "Fix for incorrect parse of PEXTRW instruction" Andreas Gampe
2015-04-09[MIPS] Refactoring code for disassembler Goran Jakovljevic
Code for mips64 is merged with code for mips. Change-Id: I2e3f2118c69a189787ae8e7f09adb4ee5c0d00d9
2015-04-07Merge "Fix address formatting in Mips64 disassembler." David Srbecky
2015-04-07Merge "Build 32-bit version of the disassembler as well." David Srbecky
2015-04-07Fix for incorrect parse of PEXTRW instruction nikolay serdjuk
The instruction PEXTRW encoded by sequence 66 0F C5 has form: PEXTRW reg, xmm, imm8. Its reg is encoded in the REG part and xmm is encoded in the R/M part of ModR/M byte. Since the order is opposite to the PEXTRB and PEXTRD, we have to set 'load' to true and 'store' leave as false. Change-Id: I32c42ea005eec29f7bf969f275c36ffa0a95fa6d
2015-04-06ART: Enable more Clang warnings Andreas Gampe
Change-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c
2015-04-06Fix address formatting in Mips64 disassembler. David Srbecky
Use FormatInstructionPointer like all the other disassemblers. This ensures that the 'absolute_addresses' option is honoured. Change-Id: I5580319cc4fad40e00f3fbbde25b142f7c689390
2015-04-06Build 32-bit version of the disassembler as well. David Srbecky
Change-Id: I22ecc2611c3b05b1031b42abdb5bf8c245220e03
2015-04-02Merge "[optimizing] Implement x86/x86_64 math intrinsics" Andreas Gampe
2015-04-01[optimizing] Implement x86/x86_64 math intrinsics Mark Mendell
Implement floor/ceil/round/RoundFloat on x86 and x86_64. Implement RoundDouble on x86_64. Add support for roundss and roundsd on both architectures. Support them in the disassembler as well. Add the instruction set features for x86, as the 'round' instruction is only supported if SSE4.1 is supported. Fix the tests to handle the addition of passing the instruction set features to x86 and x86_64. Add assembler tests for roundsd and roundss to x86_64 assembler tests. Change-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-03-31ARM64: Update to VIXL 1.9. Serban Constantinescu
Update VIXL's interface to VIXL 1.9. Change-Id: Iebae947539cbad65488b7195aaf01de284b71cbb Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
2015-03-20ART: Add Mips32r6 backend support Douglas Leung
Add Mips32r6 compiler support. Don't use deprecated Mips32r2 instructions if running in Mips32r6 mode. Change-Id: I54e689aa8c026ccb75c4af515aa2794f471c9f67
2015-03-06Initial support for quick compiler on MIPS64r6. Maja Gagic
Change-Id: I6f43027b84e4a98ea320cddb972d9cf39bf7c4f8
2015-03-06ART: Enable the use of relative addresses in the arm64 disassembler. Alexandre Rames
Also, only keep register aliases for the link register 'lr' and the thread register 'tr' in the arm64 disassembler. Other aliases are not very important, and this way we don't have to provide aliases specialised for Quick or Optimizing. Change-Id: Ie7a04910f0c587710a0cf2648203d7e89eab5d1f
2015-02-28ART: Fix Mips disassembler for some floating point instructions. Douglas Leung
Change-Id: I2b661a8dae4cd924c081df85f570007cf645769c
2015-02-03ARM/ARM64: Dump thread offset. Zheng Xu
Dump thread offset in compiler verbose log for arm32/arm64 and oatdump for arm64. Before patch : 0x4e: ldr lr, [rSELF, #604] After patch : 0x4e: ldr lr, [rSELF, #604] ; pTestSuspend Change-Id: I514e69dc44b1cf4c8a8fa085b31f93cf6a1b7c91
2015-02-02Merge "ART: Fix x86 disassembler" Andreas Gampe
2015-01-30Add options for building/testing with coverage. Dan Albert
acov --clean mm -B NATIVE_COVERAGE=true ART_COVERAGE=true test-art-host acov --host -B is needed because you need to be sure you rebuild *all* of ART with coverage. Change-Id: Ib94ef610bd1b44dc45624877710ed733051b7a50
2015-01-29Remove libcxx.mk cruft. Dan Albert
This is on by default now. No need to leave it in the makefiles. Change-Id: I20eab7426da4bbbf8b70ffc5b9af7b97487d885d
2015-01-27ART: Fix x86 disassembler Andreas Gampe
Index 4 in SIB is valid when given Rex.x, where it denotes r12 and not the invalid rsp. Bug: 19149560 Change-Id: I1a74bcbb1ccf3686e45a3df5d852a86444f9d850
2015-01-15ART: Allow to compile interpret-only mips64 files Andreas Gampe
Include enough infrastructure to allow cross-compiling for mips64, interpret-only. This includes the instruction-set-features, frame size info and utils assembler. Also add a disassembler for oatdump, and support in patchoat. Note: the runtime cannot run mips64, yet. Change-Id: Id106581fa76b478984741c62a8a03be0f370d992
2015-01-13ART: Use jalr instead of jr for Mips Andreas Gampe
Use the jalr instruction instead of jr in stubs and compiled code. Change-Id: Idacc5167a5bb0113dc2e7716e4767e5ed07b5e0b
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