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2015-10-30Merge "ART: Arm32 packed-switch jump tables" Andreas Gampe
2015-10-30ART: Arm32 packed-switch jump tables Andreas Gampe
Add jump table support to the thumb2 assembler. Jump tables are a collection of labels for the case targets, and an anchor label denoting the position of the jump. Use the jump table support to implement packed-switch support for arm32. Add tests for BindTrackedLabel and JumpTable to the thumb2 assembler test. Bug: 24092914 Change-Id: I5c84f193dfebf9e07f48678efc8bd151bb1410dd
2015-10-30X86: Add support for ucomis[sd] reg/memory form Mark Mendell
Allow an Address as the second operand. Change-Id: I4940829e2e4bfe0cddef3808265fdb638ac07b7e Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-10-27Reduce memory used by CompiledMethods. Vladimir Marko
Use LengthPrefixedArray<>s instead of SwapVector<>s to store CompiledMethod data and get rid of the unnecessary members of CompiledMethod to reduce dex2oat memory usage. Refactor the deduplication from CompilerDriver to a new class. Use HashSet<> instead of std::set<> for the DedupeSet<> to further decrease the memory usage and improve performance. This reduces the dex2oat memory usage when compiling boot image on Nexus 5 (with Optimizing, -j1) by ~6.75MiB (5%). This also reduces the compile time by ~2.2% (~1.6% dex2oat time; with Optimizing, without -j). Change-Id: I974f1f5e58350de2bf487a2bca3907fa05fb80ea
2015-10-23Move ArenaBitVector into the runtime Mathieu Chartier
Motivation is using arenas in the verifier. Bug: 10921004 Change-Id: I3c7ed369194b2309a47b12a621e897e0f2f65fcf
2015-10-20MIPS64: Add tests for rotation, and shift instructions Chris Larsen
Change-Id: I5611cb5c638c6be193739cbe859cb4ff4074a5fa
2015-10-19MIPS64: Add intrinsic support for bit rotation Chris Larsen
- int java.lang.Integer.rotateRight(int i, int distance) - int java.lang.Long.rotateRight(long i, int distance) Assembler tests for new MIPS instructions will be provided in a separate patch. Change-Id: I6dd4786e2d5f674bf56ff3d5afd321bb1bef589e
2015-10-16Merge "MIPS64: Additional assember tests:" Andreas Gampe
2015-10-15Use ATTRIBUTE_UNUSED more. Roland Levillain
Use it in lieu of UNUSED(), which had some incorrect uses. Change-Id: If247dce58b72056f6eea84968e7196f0b5bef4da
2015-10-14Merge "X86 jump tables for PackedSwitch" Vladimir Marko
2015-10-14Merge "X86_64 jump tables for PackedSwitch" Vladimir Marko
2015-10-14X86 jump tables for PackedSwitch Mark Mendell
Implement X86PackedSwitch using a jump table of offsets to blocks. The X86PackedSwitch version just adds an input to address the constant area. Change-Id: Id2752a1ee79222493040c6fd0e59aee9a544b76a Bug: 21119474 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-10-14X86_64 jump tables for PackedSwitch Mark Mendell
Implement PackedSwitch using a jump table of offsets to blocks. Bug: 24092914 Bug: 21119474 Change-Id: I83430086c03ef728d30d79b4022607e9245ef98f Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-10-14Merge "Improve Thumb2 bitwise operations." Vladimir Marko
2015-10-14Improve Thumb2 bitwise operations. Vladimir Marko
Allow embedding constants in AND, ORR, EOR. Add ORN to assembler, use BIC and ORN for AND and ORR when needed. Change-Id: I24d69ecc7ce6992b9c5eb7a313ff47a942de9661
2015-10-14Fix braino in arm assembler. Nicolas Geoffray
Method is pure virtual. Caught by clang. Change-Id: I061666ec919702fa7c30e9a98161cad56a9c864d
2015-10-14Merge "Implement System.arraycopy intrinsic for arm." Nicolas Geoffray
2015-10-13Implement System.arraycopy intrinsic for arm. Nicolas Geoffray
Change-Id: I58ae1af5103e281fe59fbe022b718d6d8f293a5e
2015-10-13Merge "MIPS: Assemblers changes needed for optimizing compiler" Nicolas Geoffray
2015-10-08Add DCHECKs to ArenaVector and ScopedArenaVector. Vladimir Marko
Implement dchecked_vector<> template that DCHECK()s element access and insert()/emplace()/erase() positions. Change the ArenaVector<> and ScopedArenaVector<> aliases to use the new template instead of std::vector<>. Remove DCHECK()s that have now become unnecessary from the Optimizing compiler. Change-Id: Ib8506bd30d223f68f52bd4476c76d9991acacadc
2015-10-07ART: Change asm test logging Andreas Gampe
Adapt the output a bit to log the exact shell command, and change how the output is logged and what is logged. Should get more info on failure. Change-Id: Iacf58d27d6e1cf01e2fcd5835c4e0f8b5a820501
2015-10-06MIPS64: Additional assember tests: Chris Larsen
- MOV.fmt - NEG.fmt - CVT.D.fmt - CVT.S.fmt - JALR - SLL - SRL - SRA - DSLL - DSRA - DSRL - DSLL32 - DSRL32 - DSRA32 Change-Id: Ib15ac72128805a9bca707211359191e32d95d5d7
2015-10-06ART: Add more error logging to assembler tests Andreas Gampe
Add error logging so we can figure out when something goes wrong on the build servers. Change-Id: Idf9bc1d0e19846059d1dc78510be6333179cd758
2015-10-06MIPS: Assemblers changes needed for optimizing compiler Goran Jakovljevic
Also add assembler tests for MIPS32. Change-Id: I3ab1fba7f3b06eb3b5058861946d675494a30775
2015-10-05MIPS64r6 Assembler Tests Chris Larsen
Assembler tests for: - SQRT.fmt - ABS.fmt - ROUND.L.fmt - ROUND.W.fmt - CEIL.L.fmt - CEIL.W.fmt - FLOOR.L.fmt - FLOOR.W.fmt - SEL.fmt - RINT.fmt - CLASS.fmt - MIN.fmt - MAX.fmt - cvt.d.l - BITSWAP - DBITSWAP - DSBH - DSHD - WSBH - ROTR - SELEQZ - SELNEZ - CLZ - CLO - DCLZ - DCLO - SC - SCD - LL - LLD These are the assembler instructions which were added to support intrinsic functions on MIPS64. Tests for additional assembler instructions will follow. Support added to the testing infrastructure for: - Assembler instructions which use three registers; previously instructions were limited to one, or two, registers. - Immediate values which have their sizes specified by the number of bits required to store them rather than the number of bytes, in both signed and unsigned versions. Change-Id: I38c07dcbf2539825b25bed13aac05a26fa594b0b
2015-10-01MIPS64: Code cleanup. Chris Larsen
1. Add comment to explain logic for GenMinMax in intrinsics code. 2. Declare enumerated type for class.s/class.d mask values. 3. Change intrinsics code to use the enumerated values described in item 2. 4. Change "CLASS_MASK" to "kFPLeaveUnchanged" to match ART coding standards. Change-Id: Ib1fe4b01515595b46e5f101e0082bb9bbcf0c688
2015-09-29Optimizing: Tag arena allocations in code generators. Vladimir Marko
And completely remove the deprecated GrowableArray. Replace GrowableArray with ArenaVector in code generators and related classes and tag arena allocations. Label arrays use direct allocations from ArenaAllocator because Label is non-copyable and non-movable and as such cannot be really held in a container. The GrowableArray never actually constructed them, instead relying on the zero-initialized storage from the arena allocator to be correct. We now actually construct the labels. Also avoid StackMapStream::ComputeDexRegisterMapSize() being passed null references, even though unused. Change-Id: I26a46fdd406b23a3969300a67739d55528df8bf4
2015-09-25Optimizing: Rewrite DCE's MarkReachableBlocks(). Vladimir Marko
Replace a recursive implementation with a loop using a work list to avoid stack overflow that we would presumably hit for 702-LargeBranchOffset in host debug build with -O0, once the DCE block elimination is enabled for methods containing try-catch. Bug: 24133462 Change-Id: I41288ba368722bcb5d68259c7c147552c8928099
2015-09-18Merge "Fix x64's cmpw." Nicolas Geoffray
2015-09-18Fix x64's cmpw. Nicolas Geoffray
Change-Id: If700f2994990864c8b34aa52eb7a767153a1f917
2015-09-17ART: Refactor intrinsics slow-paths Andreas Gampe
Refactor slow paths so that there is a default implementation for common cases (only arm64 with vixl is special). Write a generic intrinsic slow-path that can be reused for the specific architectures. Move helper functions into CodeGenerator so that they are accessible. Change-Id: Ibd788dce432601c6a9f7e6f13eab31f28dcb8550
2015-09-16Merge "Additional MIPS64 instructions needed by intrinsics code." Andreas Gampe
2015-09-15Add X86 bsf and rotate instructions Mark Mendell
These are for use in new intrinsics. Bsf (Bit Scan Forward) is used in {Long,Integer}NumberOfTrailingZeros and the rotates are used in {Long,Integer}Rotate{Left,Right}. Change-Id: Icb599d7e1eec4e4ea9e5b4f0b1654c7b8d4de678 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-09-14Remove unnecessary std::move from test_dex_file_builder Pirama Arumuga Nainar
This stops Clang from warning about -Wpessimizing-move. Change-Id: Id40acf1c398c615faf6486ef700df6975a5f013f
2015-09-11Merge "ARM/ARM64: Intrinsics - numberOfTrailingZeros, rotateLeft, rotateRight" Vladimir Marko
2015-09-11ARM/ARM64: Intrinsics - numberOfTrailingZeros, rotateLeft, rotateRight Scott Wakeling
Change-Id: I2a07c279756ee804fb7c129416bdc4a3962e93ed
2015-09-10Additional MIPS64 instructions needed by intrinsics code. Chris Larsen
Change-Id: If2a48300aac7a10dadf485d1765fb5bdeed975fe
2015-09-08[optimizing] Add support for x86 constant area Mark Mendell
Use the Quick trick of finding the address of the method by calling the next instruction and popping the return address into a register. This trick is used because of the lack of PC-relative addressing in 32 bit mode on the X86. Add a HX86ComputeBaseMethodAddress instruction to trigger generation of the method address, which is referenced by instructions needing access to the constant area. Add a HX86LoadFromConstantTable instruction that takes a HX86ComputeBaseMethodAddress and a HConstant that will be used to load the value when needed. Change Add/Sub/Mul/Div to detect a HX86LoadFromConstantTable right hand side, and generate code that directly references the constant area. Other uses will be added later. Change the inputs to HReturn and HInvoke(s), replacing the FP constants with HX86LoadFromConstantTable instead. This allows values to be loaded from the constant area into the right location. Port the X86_64 assembler constant area handling to the X86. Use the new per-backend optimization framework to do this conversion. Change-Id: I6d235a72238262e4f9ec0f3c88319a187f865932 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-09-08ART: Clean up Thumb2Assembler's AddConstant(). Vladimir Marko
Change-Id: I6a4c32d1bba79879e5514059df6336dc331246c1
2015-09-04Merge "ART: Abort if malloc() fails in SwapAllocator::allocate()." Vladimir Marko
2015-09-04ART: Abort if malloc() fails in SwapAllocator::allocate(). Vladimir Marko
Change-Id: I084da8d376b0a86fc551b87d77ce9c74e60359bf
2015-09-03ART: Move DexCache arrays to native. Vladimir Marko
This CL has a companion CL in libcore/ https://android-review.googlesource.com/162985 Change-Id: Icbc9e20ad1b565e603195b12714762bb446515fa
2015-09-01Merge "ART: Add 16-bit Thumb2 ROR, NEGS and CMP for high registers." Vladimir Marko
2015-09-01ART: Add 16-bit Thumb2 ROR, NEGS and CMP for high registers. Vladimir Marko
Also clean up the usage of set_cc flag. Define a SetCc enumeration that specifies whether to set or keep condition codes or whether we don't care and a 16-bit instruction should be selected if one exists. This reduces the size of Nexus 5 boot.oat by 44KiB (when compiled with Optimizing which is not the default yet). Change-Id: I047072dc197ea678bf2019c01bcb28943fa9b604
2015-08-27Merge "X86: Assembler support for near labels" Vladimir Marko
2015-08-26Merge "Minor changes to art::arm::Thumb2Assembler::StoreToOffset." Roland Levillain
2015-08-26X86: Assembler support for near labels Mark Mendell
The optimizing compiler uses 32 bit relative jumps for all forward jumps, just in case the offset is too large to fit in one byte. Some of the generated code knows that the jumps will in fact fit. Add a 'NearLabel' class to the x86 and x86_64 assemblers. This will be used to generate known short forward branches. Add jecxz/jrcxz instructions, which only handle a short offset. They will be used for intrinsics. Add tests for the new instructions and NearLabel. Change-Id: I11177f36394d35d63b32364b0e6289ee6d97de46 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
2015-08-25Minor changes to art::arm::Thumb2Assembler::StoreToOffset. Roland Levillain
- Use CHECK instead of DCHECK for consistency reasons. - Adjust documentation. - Stylistic changes. Change-Id: Ibc8261a0eb5a8b4d62edc1df0d5fb378e5021c22
2015-08-25Revert "Revert "[MIPS] Use hard float calling convention for managed code"" Goran Jakovljevic
This reverts commit 7fee84c087e0f903e7d43bef180df047db1c8051. Fixed issue with temporary registers on Mips32r6. Change-Id: I93018927e6a6036cff2d55e6cda66d3212a4316b
2015-08-21Revert "[MIPS] Use hard float calling convention for managed code" Vladimir Marko
MipsMir2Lir::LockCallTemps() is broken for secondary architecture on aosp_mips64-eng. This reverts commit a29449dcf57c57fe0876f51367985477317cc557. Change-Id: I480ea7569d73aea7894fc0a6dd804b1135286a37
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