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2020-02-13Remove MIPS support from JNI/trampoline compiler. Vladimir Marko
Also remove MIPS assembler/disassembler support. Test: aosp_taimen-userdebug boots. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Bug: 147346243 Change-Id: Id736074b97cd04987a7902741828b119508df1c0
2020-01-16jni: Do not create a managed frame for @CriticalNative. Vladimir Marko
Omit managed frame for @CriticalNative methods, do not check for exceptions and and make a tail call when possible. Pass the method pointer in a hidden argument to prepare for implementing late binding for @CriticalNative methods. This changes only the JNI compiler, Generic JNI shall be updated in a separate change. Performance improvements reported by Golem (art-opt-cc): x86 x86-64 arm arm64 NativeDowncallStaticCritical6 +17% +50% +88% +139% NativeDowncallStaticCritical +37% +32% +103% +216% Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Test: aosp_taimen-userdebug boots. Test: run-gtests.sh Test: testrunner.py --target --optimizing Bug: 112189621 Change-Id: I5758c8f478627f2eee8f615b4537a907c211b9f8
2020-01-08Disable test cases `AssemblerMIPS{32r6,64}Test.Toolchain` in ART gtest. Roland Levillain
These test cases rely on `gcc` (used as reference assembler), which is being removed from Android (b/147240075). This does not affect other test cases in `assembler_mips32r6_test` and `assembler_mips64_test`, as verification against the reference assembler had already been disabled for speed reasons (b/73903608). Test: m test-art-host-gtest-assembler_mips32r6_test Test: m test-art-host-gtest-assembler_mips64_test Bug: 147240075 Bug: 147336214 Bug: 147346243 Change-Id: I99edd834c5e3ca626b36b6cbfecfb551f01e8640
2019-03-29Modernise code to use override specifier Yi Kong
Generated by clang-tidy, with IgnoreDestructors option enabled. Test: m checkbuild Bug: 116509795 Change-Id: I5dafa10c2cf605165581b8cf7dd2633ed101ed65
2018-12-27ART: Refactor for bugprone-argument-comment Andreas Gampe
Handles compiler. Bug: 116054210 Test: WITH_TIDY=1 mmma art Change-Id: I5cdfe73c31ac39144838a2736146b71de037425e
2018-09-25Merge "Revert^2 "ART: Refactor typedef to using"" Treehugger Robot
2018-09-20ART: Modernize counting-down loops Andreas Gampe
Preparation for readability-implicit-bool-conversion. Bug: 32619234 Test: WITH_TIDY=1 mmma art Change-Id: I7a6f9636d5f4537020f99e8cf8560f7f6b6b7ba0
2018-09-20Revert^2 "ART: Refactor typedef to using" Andreas Gampe
This reverts commit ee07743e03042c2ca36e0c9513847a9e7d2509f1. Reason for revert: fixed attributes. Bug: 32619234 Test: m test-art-host Test: m test-art-target-gtest-unstarted_runtime_test Change-Id: I6f0a775adfdf6ecd132b470f7c5446e949872e20
2018-09-20Revert "ART: Refactor typedef to using" Andreas Gampe
This reverts commit 9a20ff06f7ccee08a742c315ec6d351ab56ba1cd. Reason for revert: Attributes on the wrong side. Bug: 32619234 Change-Id: I8fd2abef619b22c02ccfbf5ae629339f1a60918b
2018-09-19ART: Refactor typedef to using Andreas Gampe
Add clang-tidy's modernize-use-using. Bug: 32619234 Test: WITH_TIDY=1 mmma art Change-Id: If50d37b5152af4270784e3cde7951292a9e19033
2018-09-07ART: Continue adding override annotations Andreas Gampe
Use Clang-tidy's modernize-use-override to add more annotations. Ignore inferred annotations on destructors. Bug: 32619234 Test: mmma art Change-Id: Ic432c928e398d44df9171e42db04ee19946e6887
2018-08-28Use 'final' and 'override' specifiers directly in ART. Roland Levillain
Remove all uses of macros 'FINAL' and 'OVERRIDE' and replace them with 'final' and 'override' specifiers. Remove all definitions of these macros as well, which were located in these files: - libartbase/base/macros.h - test/913-heaps/heaps.cc - test/ti-agent/ti_macros.h ART is now using C++14; the 'final' and 'override' specifiers have been introduced in C++11. Test: mmma art Change-Id: I256c7758155a71a2940ef2574925a44076feeebf
2018-07-03ART: Do not use std::<container>::at(). Vladimir Marko
These functions are specified as throwing std::out_of_range and we do not use exceptions. Test: m Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Change-Id: I67c365ed6d779c101a18b9f386c751c48ca76e16
2018-05-08Merge "MIPS: Skip output verification for assembler tests." Vladimir Marko
2018-05-04MIPS: Skip output verification for assembler tests. Vladimir Marko
These tests were taking too much time, skipping the output verification brings it down from ~60s to ~10s per test. Test: m test-art-host-gtest Bug: 73903608 Change-Id: Ifd55c8013dea92de631e7c033111959a794759f2
2018-05-04ARM: Remove VIXL dependency from ArmManagedRegister. Vladimir Marko
Also remove unnecesary DWARF includes. Motivation: Preparing to move JNI calling conventions to runtime/ to unify the GenericJNI frame creation with the JNI compiler. Test: Rely on TreeHugger. Change-Id: If8afc4a4fa41e41f0242962bb225b36633c1c153
2018-04-26Clean up include paths David Sehr
Remove runtime/globals.h and make clients point to the right globals.h (libartbase/base/globals.h). Also make within-libartbase includes relative rather than using base/, etc. Bug: 22322814 Test: make -j 40 checkbuild Change-Id: I99de63fc851d48946ab401e2369de944419041c7
2018-04-05Move remaining runtime/base stuff to libartbase David Sehr
Move the remainder of the Arena stuff, plus dumpable and runtime/*memory_region* to libartbase. More preparation to build profiling library. Bug: 22322814 Test: make -j 50 checkbuild Change-Id: Iaf26d310c89bc58846553281576c18102f5e4122
2018-03-07MIPS: Use PCNT to implement VisitIntegerBitCount() and VisitLongBitCount() Lena Djokic
Test: ./testrunner.py --target --optimizing in QEMU Test: mma test-art-host-gtest Change-Id: I6ce5bdc86f951094f656c2f81ae8fc836d7a0b5c
2017-12-07ART: Replace base/logging with android-base/logging Andreas Gampe
Replace wherever possible. ART's base/logging is now mainly VLOG and initialization code that is unnecessary to pull in and makes changes to verbose logging more painful than they have to be. Test: m test-art-host Change-Id: I3e3a4672ba5b621e57590a526c7d1c8b749e4f6e
2017-12-04MIPS32: Fix and refactor in/out reg mask code Alexey Frunze
This is mostly for clarity and future work. This fixes the following: - aui has an out reg, not an in/out reg - maddv.df, msubv.df, fmadd.df, fmsub.df have an in/out reg, not a simply out reg This also ensures consistent marking of even-numbered 32-bit FPRs used by FPR load and store instructions (odd-numbered 32-bit FPRs remain unmarked as if there are no paired FPRs; we don't use odd-numbered 32-bit FPRs to hold single-precision values). Test: test-art-host-gtest Test: booted MIPS32R2 in QEMU Test: booted MIPS64R6 in QEMU Test: testrunner.py --target --optimizing --32 (on CI20 and MIPS32R6) Test: test-art-target-gtest32 (on CI20 and MIPS32R6) Change-Id: I408b8ac063c9b1cc6f036dda095d1e3e1e2e1ef1
2017-11-08MIPS: Add asub_s/u.df Lena Djokic
These instructions are needed for implementing Sum-of-Abs-Differences visitor. Test: mma test-art-host-gtest Change-Id: Ie708f30a450b0558215f59f21bb49b68c852f247
2017-10-23MIPS32: Improve stack alignment, use sdc1/ldc1, where possible. Chris Larsen
- Ensure that SP is a multiple of 16 at all times, and - Use ldc1/sdc1 to load/store FPU registers from/to 8-byte-aligned locations wherever possible. Use `export ART_MIPS32_CHECK_ALIGNMENT=true` when building Android to enable the new runtime alignment checks. Test: Boot & run tests on 32-bit version of QEMU, and CI-20. Test: test/testrunner/testrunner.py --target --optimizing --32 Test: test-art-host-gtest Test: test-art-target-gtest Change-Id: Ia667004573f419fd006098fcfadf5834239cb485
2017-10-19MIPS: Introduce a few MSA instructions Lena Djokic
These instructions are needed for SIMD reduction. Also added assembler tests for each instruction. Test: mma test-art-host-gtest Change-Id: I0f02618a14b4cbcc3b81ce51dd2586fa4cdbfd18
2017-10-16MIPS32R2: Enable table-based switch in presence of irreducible loops Alexey Frunze
Test: test-art-host-gtest Test: booted MIPS32R2 in QEMU Test: testrunner.py --target --optimizing --32 Test: repeat all of the above with suppressed generation of HMipsPackedSwitch Change-Id: Ic8a27d88cd2d7eebaf5826ce8fd1a5607a024844
2017-10-09Use ScopedArenaAllocator for register allocation. Vladimir Marko
Memory needed to compile the two most expensive methods for aosp_angler-userdebug boot image: BatteryStats.dumpCheckinLocked() : 25.1MiB -> 21.1MiB BatteryStats.dumpLocked(): 49.6MiB -> 42.0MiB This is because all the memory previously used by Scheduler is reused by the register allocator; the register allocator has a higher peak usage of the ArenaStack. And continue the "arena"->"allocator" renaming. Test: m test-art-host-gtest Test: testrunner.py --host Bug: 64312607 Change-Id: Idfd79a9901552b5147ec0bf591cb38120de86b01
2017-10-04Do not refresh the Marking Register in CriticalNative methods. Roland Levillain
CriticalNative methods shall not be suspended and hence do not require MR to be refreshed in compiled JNI code. This change is for ARM and ARM64 only. Impact on Critical Native benchmarks times (median of 10 runs, lower is better): * angler-userdebug - ARMv7 ** All cores NativeDowncallStaticCritical -2.78% NativeDowncallStaticCritical6 -1.79% ** Little cores only NativeDowncallStaticCritical -1.66% NativeDowncallStaticCritical6 -1.27% ** Big cores only NativeDowncallStaticCritical -2.66% NativeDowncallStaticCritical6 -1.70% * angler-userdebug - ARMv8 ** All cores NativeDowncallStaticCritical -3.52% NativeDowncallStaticCritical6 -1.79% ** Little cores only NativeDowncallStaticCritical -1.63% NativeDowncallStaticCritical6 -1.27% ** Big cores only NativeDowncallStaticCritical -3.87% NativeDowncallStaticCritical6 -1.75% Test: m test-art-target Test: m test-art-target with tree built with ART_USE_READ_BARRIER=false Test: m test-art-host-gtest Test: ARM64 device boot test Test: ARM device boot test Bug: b/37707231 Change-Id: I95d61b9ecde0afffdd5fd44763b19caa06025ec8
2017-09-19ART: Remove heap poisoning from globals.h Andreas Gampe
Remove mostly-unused include and move it to its users. Test: m Change-Id: Ibb40f919db64a490290c6e18cf1123aaf44199fc
2017-09-15Add repeat support for memory addresses. Aart Bik
Rationale: This enables exhaustive testing of instructions that use memory addresses. First use case of the generics is x86. Bug: 18380245 Bug: 18380559 Bug: 18380348 Test: assembler_x86[_64]_test Change-Id: Ib0ad6fa65477b0c6fc04642ff980a4b9543d16d5
2017-08-18MIPS32: Allow some patched instructions in delay slots Alexey Frunze
Test: test-art-host-gtest Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-gtest32 Test: testrunner.py --target --optimizing --32 Test: same tests as above on CI20 Test: booted MIPS32R2 in QEMU Change-Id: I7e1ba59993008014d0115ae20c56e0a71fef0fb0
2017-07-30MIPS: Eliminate hard-coded offsets in branches Alexey Frunze
The bulk of the change is in the assemblers and their tests. The main goal is to introduce "bare" branches to labels (as opposed to the existing bare branches with relative offsets, whose direct use we want to eliminate). These branches' delay/forbidden slots are filled manually and these branches do not promote to long (the branch target must be within reach of the individual branch instruction). The secondary goal is to add more branch tests (mainly for bare vs non-bare branches and a few extra) and refactor and reorganize the branch test code a bit. The third goal is to improve idiom recognition in the disassembler, including branch idioms and a few others. Further details: - introduce bare branches (R2 and R6) to labels, making R2 branches available for use on R6 - make use of the above in the code generators - align beqz/bnez with their GNU assembler encoding to simplify and shorten the test code - update the CFI test because of the above - add trivial tests for bare and non-bare branches (addressing existing debt as well) - add MIPS32R6 tests for long beqc/beqzc/bc (debt) - add MIPS64R6 long beqzc test (debt) - group branch tests together - group constant/literal/address-loading tests together - make the disassembler recognize: - b/beqz/bnez (beq/bne with $zero reg) - nal (bltzal with $zero reg) - bal/bgezal (bal = bgezal with $zero reg) - move (or with $zero reg) - li (ori/addiu with $zero reg) - dli (daddiu with $zero reg) - disassemble 16-bit immediate operands (in andi, ori, xori, li, dli) as signed or unsigned as appropriate - drop unused instructions (bltzl, bltzall, addi) from the disassembler as there are no plans to use them Test: test-art-host-gtest Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-gtest Test: testrunner.py --target --optimizing Test: same tests as above on CI20 Test: booted MIPS32R2 in QEMU Change-Id: I62b74a6c00ce0651528114806ba24a59ba564a73
2017-07-25MIPS: Add maddv/msubv MSA instructions Lena Djokic
Added maddv.df, msubv.df, fmadd.df and fmsub.df MSA instructions in assembler, disassembler and tests. These instructions are needed for multiplyaccumulate support in ART Vectorizer. Test: mma test-art-host-gtest Change-Id: Idef7faaeed47f1fef83fa58676ce664afe24ffe8
2017-07-19MIPS: Reduce Baker read barrier code size overhead Alexey Frunze
Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-gtest Test: testrunner.py --target --optimizing Test: same tests as above on CI20 Test: booted MIPS32 and MIPS64 in QEMU with poisoning in configurations: - with Baker read barrier thunks - without Baker read barrier thunks - ART_READ_BARRIER_TYPE=TABLELOOKUP Change-Id: I79f320bf8862a04215c76cfeff3118ebc87f7ef2
2017-07-13MIPS32: ART Vectorizer Lena Djokic
MIPS32 implementation which uses MSA extension. Note: Testing is done with checker parts of tests 640, 645, 646 and 651, locally changed to cover MIPS32 cases. These changes can't be included in this patch since MSA is not a default option. Test: ./testrunner.py --target --optimizing -j1 in QEMU (mips32r6) Change-Id: Ieba28f94c48c943d5444017bede9a5d409149762
2017-07-06MIPS32: Adds changes neccessary for saving 128 bits of data Lena Djokic
Test: mma test-art-host-gtest Test: ./testrunner.py --optimizing --target in QEMU (MIPS) Change-Id: I90b7baa1d5f910887bcc3ab80a1a48391ba80c45
2017-06-21ART: Fix old warnings Andreas Gampe
Fix Wconstant-conversion warnings. Partially reverts commit df53be273509dd43725870fb20a2c7d71f7fbfd3. Bug: 28149048 Bug: 29823425 Test: m Test: m test-art-host Change-Id: Ib377150690c0f2c2142e4b91f2144e2bcaa020ef
2017-06-09Merge "ART: Refactor bit_utils and stl_util" Treehugger Robot
2017-06-08ART: Refactor bit_utils and stl_util Andreas Gampe
Move iterator code from bit_utils.h into bit_utils_iterator.h. Move Identity into stl_util_identity.h. Remove now unnecessary includes, and fix up transitive users. Test: m Change-Id: Id1ce9cda66827c5d00584f39ed310b6b37629906
2017-06-08Introduce a number of MSA instructions for MIPS32 Lena Djokic
Added a number of MSA (The MIPS SIMD Architecture) instructions. Added assembler tests for each instruction. Test: mma test-art-host-gtest Change-Id: I1d499309fc08923484f64d1883b9c3f95eadd3be
2017-04-10MIPS: Use Lsa/Dlsa when possible. Chris Larsen
For MIPS32R6 replace instances of "sll/addu" to calculate the address of an item in an array with "lsa". For other versions of MIPS32 use the "sll/addu" sequence. Encapsulate this logic in an assembler method to eliminate having a lot of statements like "if (IsR6()) { ... } else { ... }" scattered throughout the code. MIPS64 always supports R6. This means that all instances of "dsll/daddu" used to calculate the address of an item in an array can be replaced by "dlsa" so there is no need to encapsulate conditional logic in a special method. The code can just emit "dlsa" directly. Test: mma -j2 ART_TEST_OPTIMIZING=true test-art-target-run-test Tested on MIPS32, and MIPS64 QEMU. Test: "make test-art-target-gtest32" on CI20 board. Test: "cd art; test/testrunner/testrunner.py --target --optimizing --32" on CI20 board. Change-Id: Ibe5facc1bc2a6a7a6584e23d3a48e163ae38077d
2017-03-03MIPS64: Refactor implicit null checks in array/field get/set Tijana Jakovljevic
Rationale: on MIPS64 64-bit loads and stores may be performed as pairs of 32-bit loads/stores. Implicit null checks must be associated with the first 32-bit load/store in a pair and not the last. This change ensures proper association of said checks (a few were done after the last 32-bit load/store in a pair) and lays ground for further improvements in array/field get/set. Additionally ported to MIPS32. Test: mma test-art-target-run-test in QEMU Test: mma test-art-host-gtest Change-Id: If2612df62c21522959e69c637a36cc4ea962a32e
2017-02-22MIPS: Implement heap poisoning in ART's Optimizing compiler. Alexey Frunze
This is in preparation for read barrier support. Bug: 12687968 Test: test-art-host-gtest Test: booted MIPS32R2 in QEMU Test: test-art-target Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target (both MIPS64R6 and MIPS32R6) Note: built with ART_HEAP_POISONING=true. Change-Id: I0e6e04ff8de2fc8ca6126388409fa218e6920734
2017-01-03MIPS32: java.lang.String.getChars Chris Larsen
Use memcpy(3) to copy characters under the assumption that memcpy() has been hand optimized for best performance on the platform being tested. Test: run-test --optimizing 020-string Test: run-test 020-string Test: run-test --no-prebuild --optimizing 020-string Test: run-test --no-prebuild 020-string Test: run-test --optimizing 082-inline-execute Test: run-test 082-inline-execute Test: run-test --no-prebuild --optimizing 082-inline-execute Test: run-test --no-prebuild 082-inline-execute Test: mma -j2 ART_TEST_OPTIMIZING=true test-art-target-run-test Test: booted MIPS32R2 emulator. Note: Tested against both the MIPS32R2, and MIPS64R6 emulators. Change-Id: I4192cf6244db120c8de5cc4932d4132acfc9740d
2016-12-06MIPS32: Pass more arguments in registers. Alexey Frunze
Specifically, use A0-A3,T0-T1 for non-floats and F8-F19 for floats. Test: booted MIPS32R2 in QEMU Test: test-art-target-run-test-optimizing (MIPS32R2) on CI20 Test: test-art-target-gtest (MIPS32R2) on CI20 Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-run-test-optimizing (MIPS32R6) in QEMU Test: test-art-target-gtest (MIPS32R6) in QEMU Test: test-art-host-gtest Change-Id: Ib8b0310a109d9f3d70119c1e605e54b013e60728
2016-11-04ART: Use references in assembler tests Andreas Gampe
Move parameters to const references. Bug: 32619234 Test: m Change-Id: Ib68bdc313b91fee1e9e4e1e794eeca630837b005
2016-10-20MIPS32: Implement HSelect Alexey Frunze
Test: booted MIPS32R2 in QEMU Test: test-art-target-run-test-optimizing (MIPS32R2) on CI20 Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-run-test-optimizing (MIPS32R6) in QEMU Test: test-art-host-gtest Change-Id: I8a8127d8d29cb5df84ed6f4fd4478f8d889e5cb7
2016-10-13jni: Add read barrier fast path to jni compiler Igor Murashkin
Static method dispatch via JNI requires a read barrier for the ArtMethod::GetDeclaringClass() load before adding it to the JNI StackHandleScope. We used to call ReadBarrierJni unconditionally but add a branch to skip calling it if the GC is not currently in the marking phase. Test: ART_USE_READ_BARRIER=true make test-art-host test-art-target Bug: 30437917 Change-Id: I4f505ebde17c0a67209c7bb51b3f39e37a06373a
2016-09-15MIPS32: Improve storing of constants in fields and array elements Alexey Frunze
Test: booted MIPS32 in QEMU Test: test-art-target-run-test-optimizing on CI20 Test: test-art-host-gtest Change-Id: Ifcf8c1e215e3768711c391e8da6f663bba71f8d9
2016-09-14MIPS32: Implement table-based packed switch Alexey Frunze
Test: booted MIPS32R2 in QEMU Test: test-art-target-run-test-optimizing (MIPS32R2) on CI20 Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-run-test-optimizing (MIPS32R6) in QEMU Test: test-art-host-gtest Change-Id: I2e1a65ff1ba9406b84351ba7998f853b1ce4aef9
2016-08-30MIPS32: Fill branch delay slots Alexey Frunze
Test: booted MIPS32 in QEMU Test: test-art-host-gtest Test: test-art-target-gtest Test: test-art-target-run-test-optimizing on CI20 Change-Id: I727e80753395ab99fff004cb5d2e0a06409150d7
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