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2020-02-13Remove MIPS support from JNI/trampoline compiler. Vladimir Marko
Also remove MIPS assembler/disassembler support. Test: aosp_taimen-userdebug boots. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Bug: 147346243 Change-Id: Id736074b97cd04987a7902741828b119508df1c0
2020-01-16jni: Do not create a managed frame for @CriticalNative. Vladimir Marko
Omit managed frame for @CriticalNative methods, do not check for exceptions and and make a tail call when possible. Pass the method pointer in a hidden argument to prepare for implementing late binding for @CriticalNative methods. This changes only the JNI compiler, Generic JNI shall be updated in a separate change. Performance improvements reported by Golem (art-opt-cc): x86 x86-64 arm arm64 NativeDowncallStaticCritical6 +17% +50% +88% +139% NativeDowncallStaticCritical +37% +32% +103% +216% Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Test: aosp_taimen-userdebug boots. Test: run-gtests.sh Test: testrunner.py --target --optimizing Bug: 112189621 Change-Id: I5758c8f478627f2eee8f615b4537a907c211b9f8
2018-12-27ART: Refactor for bugprone-argument-comment Andreas Gampe
Handles compiler. Bug: 116054210 Test: WITH_TIDY=1 mmma art Change-Id: I5cdfe73c31ac39144838a2736146b71de037425e
2018-09-25Merge "Revert^2 "ART: Refactor typedef to using"" Treehugger Robot
2018-09-20ART: Modernize counting-down loops Andreas Gampe
Preparation for readability-implicit-bool-conversion. Bug: 32619234 Test: WITH_TIDY=1 mmma art Change-Id: I7a6f9636d5f4537020f99e8cf8560f7f6b6b7ba0
2018-09-20Revert^2 "ART: Refactor typedef to using" Andreas Gampe
This reverts commit ee07743e03042c2ca36e0c9513847a9e7d2509f1. Reason for revert: fixed attributes. Bug: 32619234 Test: m test-art-host Test: m test-art-target-gtest-unstarted_runtime_test Change-Id: I6f0a775adfdf6ecd132b470f7c5446e949872e20
2018-09-20Revert "ART: Refactor typedef to using" Andreas Gampe
This reverts commit 9a20ff06f7ccee08a742c315ec6d351ab56ba1cd. Reason for revert: Attributes on the wrong side. Bug: 32619234 Change-Id: I8fd2abef619b22c02ccfbf5ae629339f1a60918b
2018-09-19ART: Refactor typedef to using Andreas Gampe
Add clang-tidy's modernize-use-using. Bug: 32619234 Test: WITH_TIDY=1 mmma art Change-Id: If50d37b5152af4270784e3cde7951292a9e19033
2018-07-03ART: Do not use std::<container>::at(). Vladimir Marko
These functions are specified as throwing std::out_of_range and we do not use exceptions. Test: m Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Change-Id: I67c365ed6d779c101a18b9f386c751c48ca76e16
2018-04-05Move remaining runtime/base stuff to libartbase David Sehr
Move the remainder of the Arena stuff, plus dumpable and runtime/*memory_region* to libartbase. More preparation to build profiling library. Bug: 22322814 Test: make -j 50 checkbuild Change-Id: Iaf26d310c89bc58846553281576c18102f5e4122
2018-03-07MIPS: Use PCNT to implement VisitIntegerBitCount() and VisitLongBitCount() Lena Djokic
Test: ./testrunner.py --target --optimizing in QEMU Test: mma test-art-host-gtest Change-Id: I6ce5bdc86f951094f656c2f81ae8fc836d7a0b5c
2017-12-04MIPS32: Fix and refactor in/out reg mask code Alexey Frunze
This is mostly for clarity and future work. This fixes the following: - aui has an out reg, not an in/out reg - maddv.df, msubv.df, fmadd.df, fmsub.df have an in/out reg, not a simply out reg This also ensures consistent marking of even-numbered 32-bit FPRs used by FPR load and store instructions (odd-numbered 32-bit FPRs remain unmarked as if there are no paired FPRs; we don't use odd-numbered 32-bit FPRs to hold single-precision values). Test: test-art-host-gtest Test: booted MIPS32R2 in QEMU Test: booted MIPS64R6 in QEMU Test: testrunner.py --target --optimizing --32 (on CI20 and MIPS32R6) Test: test-art-target-gtest32 (on CI20 and MIPS32R6) Change-Id: I408b8ac063c9b1cc6f036dda095d1e3e1e2e1ef1
2017-11-08MIPS: Add asub_s/u.df Lena Djokic
These instructions are needed for implementing Sum-of-Abs-Differences visitor. Test: mma test-art-host-gtest Change-Id: Ie708f30a450b0558215f59f21bb49b68c852f247
2017-10-23MIPS32: Improve stack alignment, use sdc1/ldc1, where possible. Chris Larsen
- Ensure that SP is a multiple of 16 at all times, and - Use ldc1/sdc1 to load/store FPU registers from/to 8-byte-aligned locations wherever possible. Use `export ART_MIPS32_CHECK_ALIGNMENT=true` when building Android to enable the new runtime alignment checks. Test: Boot & run tests on 32-bit version of QEMU, and CI-20. Test: test/testrunner/testrunner.py --target --optimizing --32 Test: test-art-host-gtest Test: test-art-target-gtest Change-Id: Ia667004573f419fd006098fcfadf5834239cb485
2017-10-19MIPS: Introduce a few MSA instructions Lena Djokic
These instructions are needed for SIMD reduction. Also added assembler tests for each instruction. Test: mma test-art-host-gtest Change-Id: I0f02618a14b4cbcc3b81ce51dd2586fa4cdbfd18
2017-10-16MIPS32R2: Enable table-based switch in presence of irreducible loops Alexey Frunze
Test: test-art-host-gtest Test: booted MIPS32R2 in QEMU Test: testrunner.py --target --optimizing --32 Test: repeat all of the above with suppressed generation of HMipsPackedSwitch Change-Id: Ic8a27d88cd2d7eebaf5826ce8fd1a5607a024844
2017-10-04Do not refresh the Marking Register in CriticalNative methods. Roland Levillain
CriticalNative methods shall not be suspended and hence do not require MR to be refreshed in compiled JNI code. This change is for ARM and ARM64 only. Impact on Critical Native benchmarks times (median of 10 runs, lower is better): * angler-userdebug - ARMv7 ** All cores NativeDowncallStaticCritical -2.78% NativeDowncallStaticCritical6 -1.79% ** Little cores only NativeDowncallStaticCritical -1.66% NativeDowncallStaticCritical6 -1.27% ** Big cores only NativeDowncallStaticCritical -2.66% NativeDowncallStaticCritical6 -1.70% * angler-userdebug - ARMv8 ** All cores NativeDowncallStaticCritical -3.52% NativeDowncallStaticCritical6 -1.79% ** Little cores only NativeDowncallStaticCritical -1.63% NativeDowncallStaticCritical6 -1.27% ** Big cores only NativeDowncallStaticCritical -3.87% NativeDowncallStaticCritical6 -1.75% Test: m test-art-target Test: m test-art-target with tree built with ART_USE_READ_BARRIER=false Test: m test-art-host-gtest Test: ARM64 device boot test Test: ARM device boot test Bug: b/37707231 Change-Id: I95d61b9ecde0afffdd5fd44763b19caa06025ec8
2017-08-18MIPS32: Allow some patched instructions in delay slots Alexey Frunze
Test: test-art-host-gtest Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-gtest32 Test: testrunner.py --target --optimizing --32 Test: same tests as above on CI20 Test: booted MIPS32R2 in QEMU Change-Id: I7e1ba59993008014d0115ae20c56e0a71fef0fb0
2017-07-30MIPS: Eliminate hard-coded offsets in branches Alexey Frunze
The bulk of the change is in the assemblers and their tests. The main goal is to introduce "bare" branches to labels (as opposed to the existing bare branches with relative offsets, whose direct use we want to eliminate). These branches' delay/forbidden slots are filled manually and these branches do not promote to long (the branch target must be within reach of the individual branch instruction). The secondary goal is to add more branch tests (mainly for bare vs non-bare branches and a few extra) and refactor and reorganize the branch test code a bit. The third goal is to improve idiom recognition in the disassembler, including branch idioms and a few others. Further details: - introduce bare branches (R2 and R6) to labels, making R2 branches available for use on R6 - make use of the above in the code generators - align beqz/bnez with their GNU assembler encoding to simplify and shorten the test code - update the CFI test because of the above - add trivial tests for bare and non-bare branches (addressing existing debt as well) - add MIPS32R6 tests for long beqc/beqzc/bc (debt) - add MIPS64R6 long beqzc test (debt) - group branch tests together - group constant/literal/address-loading tests together - make the disassembler recognize: - b/beqz/bnez (beq/bne with $zero reg) - nal (bltzal with $zero reg) - bal/bgezal (bal = bgezal with $zero reg) - move (or with $zero reg) - li (ori/addiu with $zero reg) - dli (daddiu with $zero reg) - disassemble 16-bit immediate operands (in andi, ori, xori, li, dli) as signed or unsigned as appropriate - drop unused instructions (bltzl, bltzall, addi) from the disassembler as there are no plans to use them Test: test-art-host-gtest Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-gtest Test: testrunner.py --target --optimizing Test: same tests as above on CI20 Test: booted MIPS32R2 in QEMU Change-Id: I62b74a6c00ce0651528114806ba24a59ba564a73
2017-07-25MIPS: Add maddv/msubv MSA instructions Lena Djokic
Added maddv.df, msubv.df, fmadd.df and fmsub.df MSA instructions in assembler, disassembler and tests. These instructions are needed for multiplyaccumulate support in ART Vectorizer. Test: mma test-art-host-gtest Change-Id: Idef7faaeed47f1fef83fa58676ce664afe24ffe8
2017-07-19MIPS: Reduce Baker read barrier code size overhead Alexey Frunze
Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-gtest Test: testrunner.py --target --optimizing Test: same tests as above on CI20 Test: booted MIPS32 and MIPS64 in QEMU with poisoning in configurations: - with Baker read barrier thunks - without Baker read barrier thunks - ART_READ_BARRIER_TYPE=TABLELOOKUP Change-Id: I79f320bf8862a04215c76cfeff3118ebc87f7ef2
2017-07-13MIPS32: ART Vectorizer Lena Djokic
MIPS32 implementation which uses MSA extension. Note: Testing is done with checker parts of tests 640, 645, 646 and 651, locally changed to cover MIPS32 cases. These changes can't be included in this patch since MSA is not a default option. Test: ./testrunner.py --target --optimizing -j1 in QEMU (mips32r6) Change-Id: Ieba28f94c48c943d5444017bede9a5d409149762
2017-07-06MIPS32: Adds changes neccessary for saving 128 bits of data Lena Djokic
Test: mma test-art-host-gtest Test: ./testrunner.py --optimizing --target in QEMU (MIPS) Change-Id: I90b7baa1d5f910887bcc3ab80a1a48391ba80c45
2017-06-08Introduce a number of MSA instructions for MIPS32 Lena Djokic
Added a number of MSA (The MIPS SIMD Architecture) instructions. Added assembler tests for each instruction. Test: mma test-art-host-gtest Change-Id: I1d499309fc08923484f64d1883b9c3f95eadd3be
2017-04-10MIPS: Use Lsa/Dlsa when possible. Chris Larsen
For MIPS32R6 replace instances of "sll/addu" to calculate the address of an item in an array with "lsa". For other versions of MIPS32 use the "sll/addu" sequence. Encapsulate this logic in an assembler method to eliminate having a lot of statements like "if (IsR6()) { ... } else { ... }" scattered throughout the code. MIPS64 always supports R6. This means that all instances of "dsll/daddu" used to calculate the address of an item in an array can be replaced by "dlsa" so there is no need to encapsulate conditional logic in a special method. The code can just emit "dlsa" directly. Test: mma -j2 ART_TEST_OPTIMIZING=true test-art-target-run-test Tested on MIPS32, and MIPS64 QEMU. Test: "make test-art-target-gtest32" on CI20 board. Test: "cd art; test/testrunner/testrunner.py --target --optimizing --32" on CI20 board. Change-Id: Ibe5facc1bc2a6a7a6584e23d3a48e163ae38077d
2017-02-22MIPS: Implement heap poisoning in ART's Optimizing compiler. Alexey Frunze
This is in preparation for read barrier support. Bug: 12687968 Test: test-art-host-gtest Test: booted MIPS32R2 in QEMU Test: test-art-target Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target (both MIPS64R6 and MIPS32R6) Note: built with ART_HEAP_POISONING=true. Change-Id: I0e6e04ff8de2fc8ca6126388409fa218e6920734
2017-01-03MIPS32: java.lang.String.getChars Chris Larsen
Use memcpy(3) to copy characters under the assumption that memcpy() has been hand optimized for best performance on the platform being tested. Test: run-test --optimizing 020-string Test: run-test 020-string Test: run-test --no-prebuild --optimizing 020-string Test: run-test --no-prebuild 020-string Test: run-test --optimizing 082-inline-execute Test: run-test 082-inline-execute Test: run-test --no-prebuild --optimizing 082-inline-execute Test: run-test --no-prebuild 082-inline-execute Test: mma -j2 ART_TEST_OPTIMIZING=true test-art-target-run-test Test: booted MIPS32R2 emulator. Note: Tested against both the MIPS32R2, and MIPS64R6 emulators. Change-Id: I4192cf6244db120c8de5cc4932d4132acfc9740d
2016-12-06MIPS32: Pass more arguments in registers. Alexey Frunze
Specifically, use A0-A3,T0-T1 for non-floats and F8-F19 for floats. Test: booted MIPS32R2 in QEMU Test: test-art-target-run-test-optimizing (MIPS32R2) on CI20 Test: test-art-target-gtest (MIPS32R2) on CI20 Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-run-test-optimizing (MIPS32R6) in QEMU Test: test-art-target-gtest (MIPS32R6) in QEMU Test: test-art-host-gtest Change-Id: Ib8b0310a109d9f3d70119c1e605e54b013e60728
2016-10-20MIPS32: Implement HSelect Alexey Frunze
Test: booted MIPS32R2 in QEMU Test: test-art-target-run-test-optimizing (MIPS32R2) on CI20 Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-run-test-optimizing (MIPS32R6) in QEMU Test: test-art-host-gtest Change-Id: I8a8127d8d29cb5df84ed6f4fd4478f8d889e5cb7
2016-09-14MIPS32: Implement table-based packed switch Alexey Frunze
Test: booted MIPS32R2 in QEMU Test: test-art-target-run-test-optimizing (MIPS32R2) on CI20 Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU Test: test-art-target-run-test-optimizing (MIPS32R6) in QEMU Test: test-art-host-gtest Change-Id: I2e1a65ff1ba9406b84351ba7998f853b1ce4aef9
2016-08-30MIPS32: Fill branch delay slots Alexey Frunze
Test: booted MIPS32 in QEMU Test: test-art-host-gtest Test: test-art-target-gtest Test: test-art-target-run-test-optimizing on CI20 Change-Id: I727e80753395ab99fff004cb5d2e0a06409150d7
2016-08-24MIPS32: Refactor implicit null checks in array/field get/set. Alexey Frunze
Rationale: on MIPS32 64-bit loads and stores may be performed as pairs of 32-bit loads/stores. Implicit null checks must be associated with the first 32-bit load/store in a pair and not the last. This change ensures proper association of said checks (a few were done after the last 32-bit load/store in a pair) and lays ground for further improvements in array/field get/set. Test: booted MIPS32 in QEMU Test: test-art-host-gtest Test: test-art-target-run-test-optimizing in QEMU Change-Id: I3674947c00bb17930790a7a47c9b7aadc0c030b8
2016-08-05ART: Extract macro assembler Andreas Gampe
Extract macro assembler functionality used by the JNI compiler from the assembler interface. Templatize the new interface so that type safety ensures correct usage. Change-Id: Idb9f56e5b87e43ee6a7378853d8a9f01abe156b2 Test: m test-art-host
2016-08-01ART: Convert pointer size to enum Andreas Gampe
Move away from size_t to dedicated enum (class). Bug: 30373134 Bug: 30419309 Test: m test-art-host Change-Id: Id453c330f1065012e7d4f9fc24ac477cc9bb9269
2016-07-27MIPS32: Improve string and class loads Alexey Frunze
Tested: - MIPS32 Android boots in QEMU - test-art-host-gtest - test-art-target-run-test-optimizing in QEMU, on CI20 - test-art-target-gtest on CI20 Change-Id: I70fd5d5267f8594c3b29d5a4ccf66b8ca8b09df3
2016-07-01MIPS32: Improve method invocation Alexey Frunze
Improvements include: - CodeGeneratorMIPS::GenerateStaticOrDirectCall() supports: - MethodLoadKind::kDirectAddressWithFixup (via literals) - CodePtrLocation::kCallDirectWithFixup (via literals) - MethodLoadKind::kDexCachePcRelative - 32-bit literals to support the above (not ready for general- purpose applications yet because RA is not saved in leaf methods, but is clobbered on MIPS32R2 when simulating PC-relative addressing (MIPS32R6 is OK because it has PC-relative addressing with the lwpc instruction)) - shorter instruction sequences for recursive static/direct calls Tested: - test-art-host-gtest - test-art-target-gtest and test-art-target-run-test-optimizing on: - MIPS32R2 QEMU - CI20 board - MIPS32R6 (2nd arch) QEMU Change-Id: Id5b137ad32d5590487fd154c9a01d3b3e7e044ff
2016-06-13Merge "MIPS32: Improve offset calculations in loads and stores" Treehugger Robot
2016-06-10MIPS32: Improve offset calculations in loads and stores Alexey Frunze
Change-Id: I6c3773e8bc1233bcda83d5b7254438ef69e9570d
2016-05-19Clean up JNI calling convention callee saves. Vladimir Marko
Precalculate callee saves at compile time and return them as ArrayRef<> instead of keeping then in a std::vector<>. Change-Id: I4fd7d2bbf6138dc31b0fe8554eac35b0777ec9ef
2016-03-21MIPS32: Implement UnsafeCASInt and UnsafeCASObject intrinsics. Alexey Frunze
Change-Id: Ie871763b9a36075fd3d70ee6e2e241ae1ccc36cf
2016-02-22MIPS32: Implement intrinsics from java.lang.Math: Chris Larsen
- abs(double) - abs(float) - abs(int) - abs(long) - max(double, double) - max(float, float) - max(int, int) - max(long, long) - min(double, double) - min(float, float) - min(int, int) - min(long, long) - sqrt(double) The math intrinsics: - ceil(double) - floor(double) - rint(double) - round(double) - round(float) aren't implemented because they require instructions which only exist for MIPS64, or for MIPS32r6. Change-Id: I943be3592b52a423fcb7ac40f46f38a5e2a58c50
2016-02-10MIPS32: peek*/poke*, and String.charAt intrinsics. Chris Larsen
- byte libcore.io.Memory.peekByte(long address) - short libcore.io.Memory.peekShort(long address) - int libcore.io.Memory.peekInt(long address) - long libcore.io.Memory.peekLong(long address) - void libcore.io.Memory.pokeByte(long address, byte value) - void libcore.io.Memory.pokeShort(long address, short value) - void libcore.io.Memory.pokeInt(long address, int value) - void libcore.io.Memory.pokeLong(long address, long value) - char java.lang.String.charAt(int index) Change-Id: I5ff30b61d87313d00f0fd3f0ee09f1c454f9c9fa
2016-01-14Merge "MIPS32: don't use R2+ instructions (mthc1, mfhc1) on MIPS32R1 or with ↵ Roland Levillain
32-bit FPUs."
2016-01-13MIPS32: don't use R2+ instructions (mthc1, mfhc1) on MIPS32R1 or Alexey Frunze
with 32-bit FPUs. Change-Id: If66932fb39cdd5946f6c05c82036191ad405a877
2016-01-13MIPS: Improve conversion between ints and floats. Alexey Frunze
Change-Id: I767fe9623cc14e8480c31e305725eb5221cac282
2015-12-16MIPS32: improvements in code generation (mostly 64-bit ALU ops) Alexey Frunze
Specifically: - Use the delay slot in InvokeRuntime() for direct entry points - Use kNoOutputOverlap wherever possible - Improve and/or/xor/add/sub with 64-bit integer constants - Improve 64-bit shifts by a constant amount on R2+ - More efficient load/store of 64-bit constants (especially, 0 & +0.0) Change-Id: I86d2217c8b5b8e2a9371effc2ce38b9eec62782b
2015-12-15MIPS32: Fuse long and FP compare & condition in Optimizing. Alexey Frunze
This also does a minor clean-up in the assembler and its test. Bug: 25559148 Change-Id: I9bad3c500b592a09013b56745f70752eb284a842
2015-12-10Merge "MIPS32: Improve integer division by constants" Nicolas Geoffray
2015-11-30MIPS32: Bit rotation intrinsics Chris Larsen
- int java.lang.Integer.rotateLeft(int i, int distance) - int java.lang.Integer.rotateRight(int i, int distance) - long java.lang.Long.rotateLeft(long i, int distance) - long java.lang.Long.rotateRight(long i, int distance) Change-Id: I7620ee12562c0dd55476a1d54e225c5e624cfb5b
2015-11-30MIPS32: int java.lang.*.numberOfLeadingZeros Chris Larsen
- int java.lang.Integer.numberOfLeadingZeros(int) - int java.lang.Long.numberOfLeadingZeros(long) Change-Id: Icaf746cb807863f944ff4ebb5da6e6b2846eac58
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