Age | Commit message (Collapse) | Author |
|
Test: m test-art-host-gtest
Change-Id: I0e9a0a684e4d4d0a80a343e7ac284d80f7a7bc2e
|
|
Add tests for newly added instructions
Adjust clang/objdump CLI options
Test: m art_compiler_host_tests
Test: $NATIVE_TESTS/art_compiler_host_tests_intermediates/art_compiler_host_tests
Change-Id: I3fdd831737daf844c7b03ef010d27d44056ec59d
|
|
Remove unnecessary indirection for registers in assembler
tests, including x86 and x86-64 tests.
Remove unnecessary `riscv64::` qualifications from riscv64
assembler tests.
Test: m test-art-host-gtest
Bug: 283082089
Change-Id: Ia3b85c9532e49ac6277d31304bd7cbcfb2f7c738
|
|
The code used to copy the final generated code twice: from assembler to
CodeAllocator, and then to CodeAllocator to SwapAllocator/JitMemory.
The assemblers never depended on the exact location of the generated
code, so just drop that feature.
Test: test.py
Change-Id: I8dc82e4926097092b9aac336a5a5d40f79dc62ca
|
|
Bug: 169680875
Test: mmm art
Change-Id: Ic0cc320891c42b07a2b5520a584d2b62052e7235
|
|
Test: m test-art-host-gtest
Change-Id: Ibe5998f7a26d6d0585855f9fa534982a584be4ea
|
|
Test: m test-art-host-gtest
Bug: 271573990
Signed-off-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Wendong Wang <wangwd@xcvmbyte.com>
Signed-off-by: Cao Xia <caoxia@eswincomputing.com>
Change-Id: I51a5c17f0d1d4e10d3b3b2f4e2ae88a75ca13bd1
|
|
Test: m test-art-host-gtest
Bug: 271573990
Signed-off-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Wendong Wang <wangwd@xcvmbyte.com>
Signed-off-by: Cao Xia <caoxia@eswincomputing.com>
Change-Id: Ie1306521b8df28173b9be40f754e114bd849985b
|
|
Test: m test-art-host-gtest
Test: testrunner.py --host --optimizing
Change-Id: I5e39375f16e0ff1372c35fda444a4ef33bf320bf
|
|
All the // NOLINT comments introduced in this CL were meant
to disable only the modernize-use-using checks, but changing
the comment to be // NOLINT(modernize-use-using) as explained
in https://clang.llvm.org/extra/clang-tidy/#suppressing-undesired-diagnostics
will make cpplint throw an error, as also cpplint uses the
// NOLINT(...) notation to suppress unwanted warnings.
Test: m tidy-art
Test: art/libnativebridge/tests/runtests.sh
Bug: 213953102
Change-Id: I9a992e0f0ecd06f7e64fd0bbf473bec4582370f6
|
|
Test: m tidy-art
Bug: 213953102
Change-Id: Ibe16d59559d96e0a4562ecd2af1dffa28bafc068
|
|
Previously tests were disabled for `xchgl reg, reg` variant with all
register pairs, although the problematic case is only `xchg eax, eax`.
This commit allows one to pass an exception list to a testing function
and skip the problematic register pairs instead of disabling the whole
test. The patch adds exception lists to all testing functions that run
over register pairs, although XCHG only needs it for `Repeatrr`.
Enabling the test revealed a few small errors in the XCHG implementation
(namely, source and destination registers were swapped, which does not
affect the result). This commit fixes the implementation so that the
tests pass.
Bug: 65872996
Test: m test-art-host-gtest
Change-Id: Iaa759861330bcfb30db1a8219b805cc479cc3280
|
|
Simplify the code in preparation of move to LLVM prebuilt tools.
Bug: 147817558
Test: m test-art-host-gtest
Change-Id: Iba277235255fd7d7f0965749b0b2d4a9567ced1f
|
|
This reverts commit 22872da653053bb4b86fbef67163a9f6b7aee25b.
Reason for revert: Checking if this CL is cause of b/160132136
Bug: 147817558
Bug: 160132136
Change-Id: Ifb6f2292292a7f69fbd0f2e9204fd37dbca84277
|
|
Add more libraries and tools to the shared ART directory in testcases.
Change the tests environment setup, so that it can find the tools.
Vast majority of tests pass. Some individual tests still need fixing.
Bug: 147817558
Test: run gtests in forrest
Change-Id: I3214f532436828c2a1a5a543e69d6b9bcf1e42af
|
|
Remove all uses of macros 'FINAL' and 'OVERRIDE' and replace them with
'final' and 'override' specifiers. Remove all definitions of these
macros as well, which were located in these files:
- libartbase/base/macros.h
- test/913-heaps/heaps.cc
- test/ti-agent/ti_macros.h
ART is now using C++14; the 'final' and 'override' specifiers have
been introduced in C++11.
Test: mmma art
Change-Id: I256c7758155a71a2940ef2574925a44076feeebf
|
|
Make ArenaPool an abstract base class and leave MallocArenaPool
implementation with it. This enables arena_allocator to be free
of MemMap, Mutex, etc., in preparation to move the remaining collections
out of runtime/base to libartbase/base.
Bug: 22322814
Test: make -j 50 test-art-host
build and boot
Change-Id: Ief84dcbfb749165d9bc82000c6b8f96f93052422
|
|
Cleanup errors from upstream cpplint in preparation
for moving art's cpplint fork to upstream tip-of-tree cpplint.
Test: cd art && mm
Bug: 68951293
Change-Id: I15faed4594cbcb8399850f8bdee39d42c0c5b956
|
|
These instructions are needed for SIMD reduction.
Also added assembler tests for each instruction.
Test: mma test-art-host-gtest
Change-Id: I0f02618a14b4cbcc3b81ce51dd2586fa4cdbfd18
|
|
Memory needed to compile the two most expensive methods for
aosp_angler-userdebug boot image:
BatteryStats.dumpCheckinLocked() : 21.1MiB -> 20.2MiB
BatteryStats.dumpLocked(): 42.0MiB -> 40.3MiB
This is because all the memory previously used by the graph
builder is reused by later passes.
And finish the "arena"->"allocator" renaming; make renamed
allocator pointers that are members of classes const when
appropriate (and make a few more members around them const).
Test: m test-art-host-gtest
Test: testrunner.py --host
Bug: 64312607
Change-Id: Ia50aafc80c05941ae5b96984ba4f31ed4c78255e
|
|
Memory needed to compile the two most expensive methods for
aosp_angler-userdebug boot image:
BatteryStats.dumpCheckinLocked() : 25.1MiB -> 21.1MiB
BatteryStats.dumpLocked(): 49.6MiB -> 42.0MiB
This is because all the memory previously used by Scheduler
is reused by the register allocator; the register allocator
has a higher peak usage of the ArenaStack.
And continue the "arena"->"allocator" renaming.
Test: m test-art-host-gtest
Test: testrunner.py --host
Bug: 64312607
Change-Id: Idfd79a9901552b5147ec0bf591cb38120de86b01
|
|
Rationale:
This enables exhaustive testing of instructions
that use various memory addressing modes and
register views (full, half, quarter, etc.).
Bug: 18380245
Bug: 18380559
Bug: 18380348
Test: assembler_x86[_64]_test
Change-Id: I598c3e35a4791166ab629479ccb969ef3c6494b8
|
|
Rationale:
This enables exhaustive testing of instructions
that use memory addresses. First use case of
the generics is x86.
Bug: 18380245
Bug: 18380559
Bug: 18380348
Test: assembler_x86[_64]_test
Change-Id: Ib0ad6fa65477b0c6fc04642ff980a4b9543d16d5
|
|
Rationale:
Quis custodiet ipsos custodes?
Therefore, it is good to make sure that the drivers
used to test the assembler are doing what is expected.
This also prepares some upcoming improvements wrt.
addressing modes and different register sizes.
Bug: 18380245
Bug: 18380559
Bug: 18380245
Test: assembler_x86[_64]_test
Change-Id: Iadc269c14cb9e15941ec66c362d59d42e9017001
|
|
Let clang-format reorder the header includes.
Derived with:
* .clang-format:
BasedOnStyle: Google
IncludeIsMainRegex: '(_test|-inl)?$'
* Steps:
find . -name '*.cc' -o -name '*.h' | xargs sed -i.bak -e 's/^#include/ #include/' ; git commit -a -m 'ART: Include cleanup'
git-clang-format -style=file HEAD^
manual inspection
git commit -a --amend
Test: mmma art
Change-Id: Ia963a8ce3ce5f96b5e78acd587e26908c7a70d02
|
|
Also fixes RepeatTemplatedRegisterImmBits template.
Test: mma test-art-host-gtest
Change-Id: Ib23f8a65ba924623f8c3a2d75d4ec4491d18feb0
|
|
This reverts commit 219bf253e5158c4f3438e70864b8bf7235c1e193.
Fixed memory leak in assembler_mips64_test.cc.
Test: mma valgrind-test-art-host-gtest-assembler_mips64_test64
Change-Id: I238833fd4555623c2716432fc67eab7696f1e28e
|
|
This reverts commit dcabc8b740bf3066d59348ffdf21c164d2b27cb4.
Reason:
FAILING TESTS
valgrind-test-art-host-gtest-assembler_mips64_test32
ninja: build stopped: subcommand failed.
19:36:36 ninja failed with: exit status 1
make: *** [run_soong_ui] Error 1
Change-Id: If658375528d2a0f34bb6b22b6565fab1d863b3f5
|
|
Added a number of MSA (The MIPS SIMD Architecture) instructions.
Added assembler tests for each instruction.
Made necessary changes in disassembler for these instructions.
Test: mma test-art-host-gtest
Change-Id: I380f02c6ae5424a96ad999037153228acb07a108
|
|
Test: run-test --64 --optimizing 020-string
Test: run-test --64 020-string
Test: run-test --64 --no-prebuild --optimizing 020-string
Test: run-test --64 --no-prebuild 020-string
Test: run-test --64 --optimizing 082-inline-execute
Test: run-test --64 082-inline-execute
Test: run-test --64 --no-prebuild --optimizing 082-inline-execute
Test: run-test --64 --no-prebuild 082-inline-execute
Test: mma -j2 ART_TEST_OPTIMIZING=true test-art-target-run-test
Test: mma test-art-target-gtest -j2
Test: booted MIPS64R6 emulator.
Note: All tests run against MIPS64 QEMU.
Change-Id: I48b9a87465f2516044a2e4f598cc5dce56b0d1c9
|
|
Move parameters to const references.
Bug: 32619234
Test: m
Change-Id: Ib68bdc313b91fee1e9e4e1e794eeca630837b005
|
|
Test: booted MIPS32R2 in QEMU
Test: test-art-target-run-test-optimizing (MIPS32R2) on CI20
Test: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU
Test: test-art-target-run-test-optimizing (MIPS32R6) in QEMU
Test: test-art-host-gtest
Change-Id: I8a8127d8d29cb5df84ed6f4fd4478f8d889e5cb7
|
|
Test: ART gtest assembler_mips_test
Change-Id: Iafedfafe6ccd76127461d66dfa7984f196be6bd2
|
|
Change-Id: Iee3f4447a6182a769490b3235abeea9551111193
|
|
And clean up some APIs to return std::unique_ptr<> instead
of raw pointers that don't communicate ownership.
Change-Id: I3017302307a0253d661240750298802fb0d9585e
|
|
This also does a minor clean-up in the assembler and
its test.
Bug: 25559148
Change-Id: I9bad3c500b592a09013b56745f70752eb284a842
|
|
Change-Id: I618c960bd211048166d9fde78d4106bd3ca42b3a
|
|
|
|
- MOV.fmt - NEG.fmt - CVT.D.fmt - CVT.S.fmt
- JALR - SLL - SRL - SRA
- DSLL - DSRA - DSRL - DSLL32
- DSRL32 - DSRA32
Change-Id: Ib15ac72128805a9bca707211359191e32d95d5d7
|
|
Also add assembler tests for MIPS32.
Change-Id: I3ab1fba7f3b06eb3b5058861946d675494a30775
|
|
Assembler tests for:
- SQRT.fmt - ABS.fmt - ROUND.L.fmt - ROUND.W.fmt
- CEIL.L.fmt - CEIL.W.fmt - FLOOR.L.fmt - FLOOR.W.fmt
- SEL.fmt - RINT.fmt - CLASS.fmt - MIN.fmt
- MAX.fmt - cvt.d.l - BITSWAP - DBITSWAP
- DSBH - DSHD - WSBH - ROTR
- SELEQZ - SELNEZ - CLZ - CLO
- DCLZ - DCLO - SC - SCD
- LL - LLD
These are the assembler instructions which were added to support
intrinsic functions on MIPS64. Tests for additional assembler
instructions will follow.
Support added to the testing infrastructure for:
- Assembler instructions which use three registers; previously
instructions were limited to one, or two, registers.
- Immediate values which have their sizes specified by the number of
bits required to store them rather than the number of bytes, in both
signed and unsigned versions.
Change-Id: I38c07dcbf2539825b25bed13aac05a26fa594b0b
|
|
This reverts commit fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98.
Adjust block label positions. Bad catch block labels were the
reason for the revert.
Change-Id: Ia6950d639d46b9da6b07f3ade63ab46d03d63310
|
|
This reverts commit f38caa68cce551fb153dff37d01db518e58ed00f.
Change-Id: Id88b82cc949d288cfcdb3c401b96f884b777fc40
Reason: broke the tests.
|
|
Change-Id: Iecc91418bb4ee1c957f42fefb737d0ee2ba960e7
|
|
Split out the part that compares a buffer with the product of a
host assembler. That will allow to reuse this for the Quick
assemblers.
Change-Id: Ie15777cb0a22f7532d8a8ea35403db0f229cd26f
|
|
This patch sets the rex prefix for the source byte register of
movzxb, movsxb, and movb that has the destination memory operand,
when the register is SPL, BPL, SIL, DIL.
This patch adds tests for movzxb and movsxb via Repeatrb(),
and adds the tertiary and quaternary register views for word and
byte registers on x86_64.
TODO: Support tests with memory operands.
Change-Id: I0c5c727f3dd4a75af039b87f7e57d0741e689038
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
|
|
Implement floor/ceil/round/RoundFloat on x86 and x86_64.
Implement RoundDouble on x86_64.
Add support for roundss and roundsd on both architectures. Support them
in the disassembler as well.
Add the instruction set features for x86, as the 'round' instruction is
only supported if SSE4.1 is supported.
Fix the tests to handle the addition of passing the instruction set
features to x86 and x86_64.
Add assembler tests for roundsd and roundss to x86_64 assembler tests.
Change-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
|
|
Add a flag. Enable commented-out code.
Change-Id: Ife17b72f2b93c128992d757e58b0e51431a3edf8
|
|
|
|
Added SHL, SHR, USHR for arm, x86, x86_64.
Change-Id: I971f594e270179457e6958acf1401ff7630df07e
|