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2024-08-02ART: Suppress -Wdeprecated-declarations for vixl includes. Vladimir Marko
Test: m Change-Id: I7152bdbcfcf7de463a237082e2f769172bb8b37a
2023-06-21Remove CodeAllocator and the extra copy of generated code. Nicolas Geoffray
The code used to copy the final generated code twice: from assembler to CodeAllocator, and then to CodeAllocator to SwapAllocator/JitMemory. The assemblers never depended on the exact location of the generated code, so just drop that feature. Test: test.py Change-Id: I8dc82e4926097092b9aac336a5a5d40f79dc62ca
2023-05-22Use C++17's [[maybe_unused]] attribute in ART Stefano Cianciulli
Bug: 169680875 Test: mmm art Change-Id: Ic0cc320891c42b07a2b5520a584d2b62052e7235
2023-03-30arm/arm64: Minor cleanup in assemblers. Vladimir Marko
Test: m test-art-host-gtest Change-Id: Ic1ca6fa6c5ec954be9de0dfab49e3c47ade4fd69
2022-11-09Make compiler/utils/ symbols hidden. Vladimir Marko
Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Change-Id: I5e39375f16e0ff1372c35fda444a4ef33bf320bf
2021-02-05ARM64: Support SVE VL other than 128-bit. Artem Serov
Arm SVE register size is not fixed and can be a multiple of 128 bits. To support that the patch removes explicit assumptions on the SIMD register size to be 128 bit from the vectorizer and code generators and enables configurable SVE vector length autovectorization, e.g. extends SIMD register save/restore routines. Test: art SIMD tests on VIXL simulator. Test: art tests on FVP (steps in test/README.arm_fvp.md) with FVP arg: -C SVE.ScalableVectorExtension.veclen=[2,4] (SVE vector [128,256] bits wide) Change-Id: Icb46e7eb17f21d3bd38b16dd50f735c29b316427
2020-11-16Revert^2 "ART: Fix breaking changes from recent VIXL update." Artem Serov
This reverts commit eeaf47f7c9bbad29afab84a0f199a5751d9c616b. Also fixes the gtest failure when VIXL simulator stack was overflown. Test: test-art-target, test-art-host. Test: ART_USE_READ_BARRIER=false \ SANITIZE_HOST=address \ ASAN_OPTIONS='detect_leaks=0' \ SOONG_ALLOW_MISSING_DEPENDENCIES=true \ ART_HEAP_POISONING=true m test-art-host-gtest Change-Id: Ibc1f21204940083879f767d6993127bdde8326af
2020-10-28Revert "ART: Fix breaking changes from recent VIXL update." Ulyana Trafimovich
Revert submission 1331125-VIXL_UPDATE_SVE Reason for revert: broken build git_master-art-host/art-gtest-heap-poisoning @ 6936943 Reverted Changes: Ic10af84a0:Merge remote-tracking branch 'aosp/upstream-master... I752a0b0ba:ART: Fix breaking changes from recent VIXL update.... Bug: 171879890 Change-Id: Idb0d5c2e88948d799a4ef2c828be2828ea2270ea
2020-10-28ART: Fix breaking changes from recent VIXL update. Artem Serov
Also fixes the vixl-related headers includes. Test: test-art-target, test-art-host Change-Id: I752a0b0baf741aa2a0693253155042104c8b3b27
2020-06-09arm/arm64: Clean up intrinsic slow paths. Vladimir Marko
Generalize and use the slow path template IntrinsicSlowPath from intrinsics_utils.h. Test: m test-art-host-gtest Test: testrunner.py --host --optimizing Test: aosp_taimen-userdebug boot image is unchanged. Change-Id: Ia8fa4e1b31c1f190fc5f02671336caec15e4cf4d
2019-10-31ARM64: Move from FPRegister to VRegister based API Evgeny Astigeevich
VIXL has had FPRegister as an alias for VRegister for backward compatibility. In the latest upstream VIXL the alias has been removed and all FPRegister based API has became VRegister based. As AOSP VIXL is being updated to the latest upstream VIXL all uses of FPRegister based API must be replaced with VRegister based API. This CL moves ART from FPRegister based API to VRegister based API. Test: test.py --host --optimizing --jit --gtest Test: test.py --target --optimizing --jit Test: run-gtests.sh Change-Id: I12541c16d0557835ea19c8667ae18c6601359b05
2019-07-18ARM/ARM64: Improve frame entry/exit codegen. Vladimir Marko
On ARM64, use STP pre-index for the method and the lowest spilled core register for method entry if there's no gap or FP spills in between. On exit, use LDP post-index to restore in this case, ignoring the method by loading to XZR. Thus, we save one instruction for both entry end exit for such methods and the performance should be the same or better. On ARM, use a single PUSH/POP for method entry and core spills if the gap between them is 2 words or less and and we have one or no FP spill, spill args as filler if needed. On exit, load the FP spill if any and do a single POP for core registers and return in this situation, clobbering as many registers from r2-r4 as needed; these caller-save registers are not used to pass return values. If we cannot do this because of FP spills but the gap between the method and FP spills is 2 words or less, we adjust SP and save the method in one PUSH after spilling; there is no similar handling for method exit as the method does not need to be restored. This may improve or degrade performance a bit depending on the particular situation; in the worst case we PUSH/POP three additional registers as a cost for smaller code size. aosp_taimen-userdebug prebuils: - before: arm/boot*.oat: 19147484 arm64/boot*.oat: 22558344 oat/arm/services.odex: 21922256 - after: arm/boot*.oat: 19105436 (-41KiB, -0.2%) arm64/boot*.oat: 22549624 (-9KiB, -0.04%) oat/arm/services.odex: 21914128 (-8KiB, -0.04%) Test: aosp_taimen-userdebug boots. Test: run-gtests.sh Test: testrunner.py --target --optimizing Bug: 136144107 Change-Id: Id36c67b4e735418fb18bcd3269b72b25695fbaa2
2019-03-29Modernise code to use override specifier Yi Kong
Generated by clang-tidy, with IgnoreDestructors option enabled. Test: m checkbuild Bug: 116509795 Change-Id: I5dafa10c2cf605165581b8cf7dd2633ed101ed65
2018-12-03ART: ARM64: Pass ISA features to VIXL macroassembler. Artem Serov
VIXL macroassembler should be initialized properly to support Armv8.X features in order to emit corresponding instructions. Test: codegen_test.cc, relative_patcher_arm64_test. Test: test-art-host, test-art-target. Change-Id: I2f9e155c28b4d2252a3cfb19717f5d25824d5e11
2018-08-28Use 'final' and 'override' specifiers directly in ART. Roland Levillain
Remove all uses of macros 'FINAL' and 'OVERRIDE' and replace them with 'final' and 'override' specifiers. Remove all definitions of these macros as well, which were located in these files: - libartbase/base/macros.h - test/913-heaps/heaps.cc - test/ti-agent/ti_macros.h ART is now using C++14; the 'final' and 'override' specifiers have been introduced in C++11. Test: mmma art Change-Id: I256c7758155a71a2940ef2574925a44076feeebf
2017-12-07ART: Replace base/logging with android-base/logging Andreas Gampe
Replace wherever possible. ART's base/logging is now mainly VLOG and initialization code that is unnecessary to pull in and makes changes to verbose logging more painful than they have to be. Test: m test-art-host Change-Id: I3e3a4672ba5b621e57590a526c7d1c8b749e4f6e
2017-10-09Use ScopedArenaAllocator for register allocation. Vladimir Marko
Memory needed to compile the two most expensive methods for aosp_angler-userdebug boot image: BatteryStats.dumpCheckinLocked() : 25.1MiB -> 21.1MiB BatteryStats.dumpLocked(): 49.6MiB -> 42.0MiB This is because all the memory previously used by Scheduler is reused by the register allocator; the register allocator has a higher peak usage of the ArenaStack. And continue the "arena"->"allocator" renaming. Test: m test-art-host-gtest Test: testrunner.py --host Bug: 64312607 Change-Id: Idfd79a9901552b5147ec0bf591cb38120de86b01
2017-08-10Instrument ARM64 generated code to check the Marking Register. Roland Levillain
Generate run-time code in the Optimizing compiler checking that the Marking Register's value matches `self.tls32_.is.gc_marking` in debug mode (on target; and on host with JIT, or with AOT when compiling the core image). If a check fails, abort. Test: m test-art-target Test: m test-art-target with tree built with ART_USE_READ_BARRIER=false Test: ARM64 device boot test with libartd. Bug: 37707231 Change-Id: Ie9b322b22b3d26654a06821e1db71dbda3c43061
2017-07-24ART: Include cleanup Andreas Gampe
Let clang-format reorder the header includes. Derived with: * .clang-format: BasedOnStyle: Google IncludeIsMainRegex: '(_test|-inl)?$' * Steps: find . -name '*.cc' -o -name '*.h' | xargs sed -i.bak -e 's/^#include/ #include/' ; git commit -a -m 'ART: Include cleanup' git-clang-format -style=file HEAD^ manual inspection git commit -a --amend Test: mmma art Change-Id: Ia963a8ce3ce5f96b5e78acd587e26908c7a70d02
2016-08-19Add support for Baker read barriers in SystemArrayCopy intrinsics. Roland Levillain
Benchmarks (ARM64) score variations on Nexus 5X with CPU cores clamped at 960000 Hz (aosp_bullhead-userdebug build): - Ritzperf - average (lower is better): -3.03% (slightly better) - CaffeineMark - average (higher is better): +1.26% (slightly better) - DeltaBlue (lower is better): -10.50% (better) - Richards - average (lower is better): -3.36% (slightly better) - SciMark2 - average (higher is better): +0.26% (virtually unchanged) Details about Ritzperf benchmarks with meaningful variations (lower is better): - FormulaEvaluationActions.EvaluateAndApplyChanges: -13.26% (better) - FormulaEvaluationActions.EvaluateCascadingSums: -10.94% (better) - FormulaEvaluationActions.EvaluateComplexFormulas: -15.50% (better) - FormulaEvaluationActions.EvaluateFibonacci: -10.41% (better) - FormulaEvaluationActions.EvaluateLargeSums: +6.02% (worse) Boot image code size variation on Nexus 5X (aosp_bullhead-userdebug build): - total ARM64 framework Oat files size change: 107047632 bytes -> 107154128 bytes (+0.10%) - total ARM framework Oat files size change: 90932028 bytes -> 91009852 bytes (+0.09%) Test: ART host and target (ARM, ARM64) tests + Nexus 5X boot. Bug: 29516905 Bug: 29506760 Bug: 12687968 Change-Id: I85431368d09965687a0301ae2eb3c991f276ce5d
2016-08-12ARM64: VIXL: Support a newer version of VIXL. Artem Serov
Please note that compiling VIXL with -Wshadow is a known VIXL issue. This will be resolved in a later version of VIXL, when we can drop the deprecated API for getters and setters. For more info take a look at VIXL_DEPRECATED in the VIXL source code. Change-Id: Iea30b1a7b065f9b16a92c6cc7ebdc50ef068b348
2016-08-08ART: Extract JNI macro assembler for arm64 Andreas Gampe
Extract the JNI assembler parts from the regular assembler. Change-Id: I0b0ad32e18f585b75e9da0237afe082c25a1d291 Test: m test-art-target (N9)
2016-08-05ART: Extract macro assembler Andreas Gampe
Extract macro assembler functionality used by the JNI compiler from the assembler interface. Templatize the new interface so that type safety ensures correct usage. Change-Id: Idb9f56e5b87e43ee6a7378853d8a9f01abe156b2 Test: m test-art-host
2016-08-02ARM64: Make the VIXL macro assembler part of ART ARM64's assembler. Alexandre Rames
This avoids a dynamic allocation of the VIXL macro assembler. Change-Id: I4cd62678d0978f1ad6f32ea0ce7279e09152be38
2016-08-01ART: Convert pointer size to enum Andreas Gampe
Move away from size_t to dedicated enum (class). Bug: 30373134 Bug: 30419309 Test: m test-art-host Change-Id: Id453c330f1065012e7d4f9fc24ac477cc9bb9269
2016-07-15Fixes to build against new VIXL interface. Scott Wakeling
- Fix namespace usage and use of deprecated functions. - Link all dependants to new libvixl-arm64 target for now. Change-Id: Iee6f299784fd663fc2a759f3ee816fdbc511e509
2016-05-19Clean up JNI calling convention callee saves. Vladimir Marko
Precalculate callee saves at compile time and return them as ArrayRef<> instead of keeping then in a std::vector<>. Change-Id: I4fd7d2bbf6138dc31b0fe8554eac35b0777ec9ef
2016-04-15Fix: correctly destruct VIXL labels. Alexandre Rames
Bug: 27505766 Change-Id: I077465e3d308f4331e7a861902e05865f9d99835
2016-04-13Move Assemblers to the Arena. Vladimir Marko
And clean up some APIs to return std::unique_ptr<> instead of raw pointers that don't communicate ownership. Change-Id: I3017302307a0253d661240750298802fb0d9585e
2015-09-17ART: Refactor intrinsics slow-paths Andreas Gampe
Refactor slow paths so that there is a default implementation for common cases (only arm64 with vixl is special). Write a generic intrinsic slow-path that can be reused for the specific architectures. Move helper functions into CodeGenerator so that they are accessible. Change-Id: Ibd788dce432601c6a9f7e6f13eab31f28dcb8550
2015-08-12Remove unnecessary `explicit` qualifiers on constructors. Roland Levillain
Change-Id: Id12e392ad50f66a6e2251a68662b7959315dc567
2015-07-01Implement heap poisoning in ART's Optimizing compiler. Roland Levillain
- Instrument ARM, ARM64, x86 and x86-64 code generators. - Note: To turn heap poisoning on in Optimizing, set the environment variable `ART_HEAP_POISONING' to "true" before compiling ART. Bug: 12687968 Change-Id: Ib3120b38cf805a8a50207a314b9ccc90c8d93740
2015-06-22Opt compiler: Add disassembly to the '.cfg' output. Alexandre Rames
This is automatically added to the '.cfg' output when using the usual `--dump-cfg` option. Change-Id: I864bfc3a8299c042e72e451cc7730ad8271e4deb
2015-06-17Revert "Revert "ART: Implement literal pool for arm, fix branch fixup."" Vladimir Marko
This reverts commit fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98. Adjust block label positions. Bad catch block labels were the reason for the revert. Change-Id: Ia6950d639d46b9da6b07f3ade63ab46d03d63310
2015-06-16Revert "ART: Implement literal pool for arm, fix branch fixup." Vladimir Marko
This reverts commit f38caa68cce551fb153dff37d01db518e58ed00f. Change-Id: Id88b82cc949d288cfcdb3c401b96f884b777fc40 Reason: broke the tests.
2015-06-15ART: Implement literal pool for arm, fix branch fixup. Vladimir Marko
Change-Id: Iecc91418bb4ee1c957f42fefb737d0ee2ba960e7
2015-05-29Move mirror::ArtMethod to native Mathieu Chartier
Optimizing + quick tests are passing, devices boot. TODO: Test and fix bugs in mips64. Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS. Some of the savings are from removal of virtual methods and direct methods object arrays. Bug: 19264997 Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d
2015-05-26ART: Clean up arm64 kNumberOfXRegisters usage. Vladimir Marko
Avoid undefined behavior for arm64 stemming from 1u << 32 in loops with upper bound kNumberOfXRegisters. Create iterators for enumerating bits in an integer either from high to low or from low to high and use them for <arch>Context::FillCalleeSaves() on all architectures. Refactor runtime/utils.{h,cc} by moving all bit-fiddling functions to runtime/base/bit_utils.{h,cc} (together with the new bit iterators) and all time-related functions to runtime/base/time_utils.{h,cc}. Improve test coverage and fix some corner cases for the bit-fiddling functions. Bug: 13925192 Change-Id: I704884dab15b41ecf7a1c47d397ab1c3fc7ee0f7
2015-04-22Replace NULL with nullptr Mathieu Chartier
Also fixed some lines that were too long, and a few other minor details. Change-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb
2015-04-14ARM64: Remove suspend register. Zheng Xu
It also clean up build/remove frame used by JNI compiler and generates stp/ldp instead of str/ldr. Also x19 has been unblocked in both quick and optimizing compiler. Change-Id: Idbeac0942265f493266b2ef9b7a65bb4054f0e2d
2015-04-06ART: Enable more Clang warnings Andreas Gampe
Change-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c
2015-03-31ARM64: Update to VIXL 1.9. Serban Constantinescu
Update VIXL's interface to VIXL 1.9. Change-Id: Iebae947539cbad65488b7195aaf01de284b71cbb Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
2014-11-04ART: More warnings Andreas Gampe
Enable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general, and -Wunused-but-set-parameter for GCC builds. Change-Id: I81bbdd762213444673c65d85edae594a523836e5
2014-10-23ART: optimizing compiler: initial support for ARM64. Alexandre Rames
The ARM64 port uses VIXL for code generation, to which it defers work like label binding and branch resolving, register type coherency checking, and immediate values handling. Change-Id: I0a44508c0c991f472a63e67b3469cdd878fe1a68 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com> Signed-off-by: Alexandre Rames <alexandre.rames@arm.com>
2014-10-17Rename arm64 `Register` to `XRegister`. Alexandre Rames
This will avoid naming conflicts in the arm64 port of the optimizing compiler. Change-Id: Ie736ddd2ddbd2e299058256de28bad5d41c57d6f
2014-10-17Rework arm64 register codes and fix Arm64ManagedRegister tests. Alexandre Rames
Change-Id: I81ce3bc8a212c9c35be3a41b182ada87b32391ec
2014-10-09stdint types all the way! Ian Rogers
Change-Id: I4e4ef3a2002fc59ebd9097087f150eaf3f2a7e08
2014-10-09ARM64: Update code after the VIXL 1.6 release. Alexandre Rames
We now leave the assembler buffer management to VIXL. Change-Id: Ieefe83cf5cf5e1ab8c924b0e7dc03af6a55053ae
2014-09-29ART: Fix some -Wpedantic errors Andreas Gampe
Remove extra semicolons. Dollar signs in C++ identifiers are an extension. Named variadic macros are an extension. Binary literals are a C++14 feature. Enum re-declarations are not allowed. Overflow. Change-Id: I7d16b2217b2ef2959ca69de84eaecc754517714a
2014-08-22ARM64: Avoid the duplication of condition codes. Alexandre Rames