diff options
Diffstat (limited to 'src')
28 files changed, 3529 insertions, 456 deletions
diff --git a/src/asm_support.h b/src/asm_support.h index 415747e242..90ff709e98 100644 --- a/src/asm_support.h +++ b/src/asm_support.h @@ -32,7 +32,13 @@ #define THREAD_SUSPEND_COUNT_OFFSET 0 // Offset of field Thread::exception_ verified in InitCpu #define THREAD_EXCEPTION_OFFSET 8 - +#elif defined(__mips__) +#define rSUSPEND $s0 +#define rSELF $s1 +// Offset of field Thread::suspend_count_ verified in InitCpu +#define THREAD_SUSPEND_COUNT_OFFSET 0 +// Offset of field Thread::exception_ verified in InitCpu +#define THREAD_EXCEPTION_OFFSET 8 #elif defined(__i386__) // Offset of field Thread::self_ verified in InitCpu #define THREAD_SELF_OFFSET 36 diff --git a/src/compiler.cc b/src/compiler.cc index e31b9b5dda..466e2df6c4 100644 --- a/src/compiler.cc +++ b/src/compiler.cc @@ -409,12 +409,17 @@ Compiler::~Compiler() { ByteArray* Compiler::CreateResolutionStub(InstructionSet instruction_set, Runtime::TrampolineType type) { - if (instruction_set == kX86) { - return x86::X86CreateResolutionTrampoline(type); - } else { - CHECK(instruction_set == kArm || instruction_set == kThumb2); - // Generates resolution stub using ARM instruction set - return arm::ArmCreateResolutionTrampoline(type); + switch (instruction_set) { + case kArm: + case kThumb2: + return arm::ArmCreateResolutionTrampoline(type); + case kMips: + return mips::MipsCreateResolutionTrampoline(type); + case kX86: + return x86::X86CreateResolutionTrampoline(type); + default: + LOG(FATAL) << "Unknown InstructionSet: " << instruction_set; + return NULL; } } @@ -423,6 +428,8 @@ ByteArray* Compiler::CreateJniDlsymLookupStub(InstructionSet instruction_set) { case kArm: case kThumb2: return arm::CreateJniDlsymLookupStub(); + case kMips: + return mips::CreateJniDlsymLookupStub(); case kX86: return x86::CreateJniDlsymLookupStub(); default: @@ -432,12 +439,17 @@ ByteArray* Compiler::CreateJniDlsymLookupStub(InstructionSet instruction_set) { } ByteArray* Compiler::CreateAbstractMethodErrorStub(InstructionSet instruction_set) { - if (instruction_set == kX86) { - return x86::CreateAbstractMethodErrorStub(); - } else { - CHECK(instruction_set == kArm || instruction_set == kThumb2); - // Generates resolution stub using ARM instruction set - return arm::CreateAbstractMethodErrorStub(); + switch (instruction_set) { + case kArm: + case kThumb2: + return arm::CreateAbstractMethodErrorStub(); + case kMips: + return mips::CreateAbstractMethodErrorStub(); + case kX86: + return x86::CreateAbstractMethodErrorStub(); + default: + LOG(FATAL) << "Unknown InstructionSet: " << instruction_set; + return NULL; } } diff --git a/src/compiler/Frontend.cc b/src/compiler/Frontend.cc index 3aedbe9b62..78c0f94313 100644 --- a/src/compiler/Frontend.cc +++ b/src/compiler/Frontend.cc @@ -801,6 +801,21 @@ CompiledMethod* oatCompileMethod(Compiler& compiler, //cUnit->enableDebug |= (1 << kDebugDumpBitcodeFile); } #endif + if (cUnit->instructionSet == kMips) { + // Disable some optimizations for mips for now + cUnit->disableOpt |= ( + (1 << kLoadStoreElimination) | + (1 << kLoadHoisting) | + (1 << kSuppressLoads) | + (1 << kNullCheckElimination) | + (1 << kPromoteRegs) | + (1 << kTrackLiveTemps) | + (1 << kSkipLargeMethodOptimization) | + (1 << kSafeOptimizations) | + (1 << kBBOpt) | + (1 << kMatch) | + (1 << kPromoteCompilerTemps)); + } /* Are we generating code for the debugger? */ if (compiler.IsDebuggingSupported()) { cUnit->genDebugger = true; diff --git a/src/compiler/codegen/mips/MipsLIR.h b/src/compiler/codegen/mips/MipsLIR.h index 4850205174..5852b31c56 100644 --- a/src/compiler/codegen/mips/MipsLIR.h +++ b/src/compiler/codegen/mips/MipsLIR.h @@ -148,7 +148,7 @@ namespace art { #define LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r_V0, INVALID_REG, \ INVALID_SREG, INVALID_SREG} #define LOC_C_RETURN_FLOAT LOC_C_RETURN -#define LOC_C_RETURN_ALT {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r_F0, \ +#define LOC_C_RETURN_ALT {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r_V1, \ INVALID_REG, INVALID_SREG, INVALID_SREG} #define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r_RESULT0, \ r_RESULT1, INVALID_SREG, INVALID_SREG} diff --git a/src/compiler/codegen/mips/MipsRallocUtil.cc b/src/compiler/codegen/mips/MipsRallocUtil.cc index ded59f0a77..43fcc071d9 100644 --- a/src/compiler/codegen/mips/MipsRallocUtil.cc +++ b/src/compiler/codegen/mips/MipsRallocUtil.cc @@ -149,8 +149,9 @@ extern RegLocation oatGetReturnWideAlt(CompilationUnit* cUnit) extern RegLocation oatGetReturnAlt(CompilationUnit* cUnit) { - UNIMPLEMENTED(FATAL); - RegLocation res = LOC_C_RETURN; + RegLocation res = LOC_C_RETURN_ALT; + oatClobber(cUnit, res.lowReg); + oatMarkInUse(cUnit, res.lowReg); return res; } diff --git a/src/constants_mips.h b/src/constants_mips.h new file mode 100644 index 0000000000..12f73233b3 --- /dev/null +++ b/src/constants_mips.h @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_SRC_CONSTANTS_MIPS_H_ +#define ART_SRC_CONSTANTS_MIPS_H_ + +#include <iosfwd> +#include "globals.h" +#include "logging.h" +#include "macros.h" + +namespace art { +namespace mips { + +enum Register { + ZERO = 0, + AT = 1, + V0 = 2, + V1 = 3, + A0 = 4, + A1 = 5, + A2 = 6, + A3 = 7, + T0 = 8, + T1 = 9, + T2 = 10, + T3 = 11, + T4 = 12, + T5 = 13, + T6 = 14, + T7 = 15, + S0 = 16, + S1 = 17, + S2 = 18, + S3 = 19, + S4 = 20, + S5 = 21, + S6 = 22, + S7 = 23, + T8 = 24, + T9 = 25, + K0 = 26, + K1 = 27, + GP = 28, + SP = 29, + FP = 30, + RA = 31, + kNumberOfCoreRegisters = 32, + kNoRegister = -1 // Signals an illegal register. +}; +std::ostream& operator<<(std::ostream& os, const Register& rhs); + +// Values for single-precision floating point registers. +enum FRegister { + F0 = 0, + F1 = 1, + F2 = 2, + F3 = 3, + F4 = 4, + F5 = 5, + F6 = 6, + F7 = 7, + F8 = 8, + F9 = 9, + F10 = 10, + F11 = 11, + F12 = 12, + F13 = 13, + F14 = 14, + F15 = 15, + F16 = 16, + F17 = 17, + F18 = 18, + F19 = 19, + F20 = 20, + F21 = 21, + F22 = 22, + F23 = 23, + F24 = 24, + F25 = 25, + F26 = 26, + F27 = 27, + F28 = 28, + F29 = 29, + F30 = 30, + F31 = 31, + kNumberOfFRegisters = 32, + kNoFRegister = -1, +}; +std::ostream& operator<<(std::ostream& os, const FRegister& rhs); + +// Values for double-precision floating point registers. +enum DRegister { + D0 = 0, + D1 = 1, + D2 = 2, + D3 = 3, + D4 = 4, + D5 = 5, + D6 = 6, + D7 = 7, + D8 = 8, + D9 = 9, + D10 = 10, + D11 = 11, + D12 = 12, + D13 = 13, + D14 = 14, + D15 = 15, + kNumberOfDRegisters = 16, + kNumberOfOverlappingDRegisters = 16, + kNoDRegister = -1, +}; +std::ostream& operator<<(std::ostream& os, const DRegister& rhs); + +// Constants used for the decoding or encoding of the individual fields of instructions. +enum InstructionFields { + kOpcodeShift = 26, + kOpcodeBits = 6, + kRsShift = 21, + kRsBits = 5, + kRtShift = 16, + kRtBits = 5, + kRdShift = 11, + kRdBits = 5, + kShamtShift = 6, + kShamtBits = 5, + kFunctShift = 0, + kFunctBits = 6, + + kFmtShift = 21, + kFmtBits = 5, + kFtShift = 16, + kFtBits = 5, + kFsShift = 11, + kFsBits = 5, + kFdShift = 6, + kFdBits = 5, + + kBranchOffsetMask = 0x0000ffff, + kJumpOffsetMask = 0x03ffffff, +}; + +enum ScaleFactor { + TIMES_1 = 0, + TIMES_2 = 1, + TIMES_4 = 2, + TIMES_8 = 3 +}; + +class Instr { + public: + static const uint32_t kBreakPointInstruction = 0x0000000D; + + bool IsBreakPoint() { + return ((*reinterpret_cast<const uint32_t*>(this)) & 0xFC0000CF) == kBreakPointInstruction; + } + + // Instructions are read out of a code stream. The only way to get a + // reference to an instruction is to convert a pointer. There is no way + // to allocate or create instances of class Instr. + // Use the At(pc) function to create references to Instr. + static Instr* At(uintptr_t pc) { return reinterpret_cast<Instr*>(pc); } + + private: + DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); +}; + +} // namespace mips +} // namespace art + +#endif // ART_SRC_CONSTANTS_MIPS_H_ diff --git a/src/globals.h b/src/globals.h index 1eeaca26aa..8577b43969 100644 --- a/src/globals.h +++ b/src/globals.h @@ -49,7 +49,8 @@ const int kObjectAlignment = 8; const int kArmAlignment = 8; // MIPS instruction alignment. MIPS processors require code to be 4-byte aligned. -const int kMipsAlignment = 4; +// TODO: Can this be 4? +const int kMipsAlignment = 8; // X86 instruction alignment. This is the recommended alignment for maximum performance. const int kX86Alignment = 16; diff --git a/src/oat/jni/calling_convention.cc b/src/oat/jni/calling_convention.cc index e7b9cc8085..92d4f0053f 100644 --- a/src/oat/jni/calling_convention.cc +++ b/src/oat/jni/calling_convention.cc @@ -17,6 +17,7 @@ #include "calling_convention.h" #include "oat/jni/arm/calling_convention_arm.h" +#include "oat/jni/mips/calling_convention_mips.h" #include "oat/jni/x86/calling_convention_x86.h" #include "logging.h" #include "utils.h" @@ -32,11 +33,17 @@ FrameOffset CallingConvention::MethodStackOffset() { ManagedRuntimeCallingConvention* ManagedRuntimeCallingConvention::Create( bool is_static, bool is_synchronized, const char* shorty, InstructionSet instruction_set) { - if (instruction_set == kX86) { - return new x86::X86ManagedRuntimeCallingConvention(is_static, is_synchronized, shorty); - } else { - CHECK(instruction_set == kArm || instruction_set == kThumb2); - return new arm::ArmManagedRuntimeCallingConvention(is_static, is_synchronized, shorty); + switch (instruction_set) { + case kArm: + case kThumb2: + return new arm::ArmManagedRuntimeCallingConvention(is_static, is_synchronized, shorty); + case kMips: + return new mips::MipsManagedRuntimeCallingConvention(is_static, is_synchronized, shorty); + case kX86: + return new x86::X86ManagedRuntimeCallingConvention(is_static, is_synchronized, shorty); + default: + LOG(FATAL) << "Unknown InstructionSet: " << instruction_set; + return NULL; } } @@ -80,11 +87,17 @@ bool ManagedRuntimeCallingConvention::IsCurrentParamAReference() { JniCallingConvention* JniCallingConvention::Create(bool is_static, bool is_synchronized, const char* shorty, InstructionSet instruction_set) { - if (instruction_set == kX86) { - return new x86::X86JniCallingConvention(is_static, is_synchronized, shorty); - } else { - CHECK(instruction_set == kArm || instruction_set == kThumb2); - return new arm::ArmJniCallingConvention(is_static, is_synchronized, shorty); + switch (instruction_set) { + case kArm: + case kThumb2: + return new arm::ArmJniCallingConvention(is_static, is_synchronized, shorty); + case kMips: + return new mips::MipsJniCallingConvention(is_static, is_synchronized, shorty); + case kX86: + return new x86::X86JniCallingConvention(is_static, is_synchronized, shorty); + default: + LOG(FATAL) << "Unknown InstructionSet: " << instruction_set; + return NULL; } } diff --git a/src/oat/jni/jni_compiler.cc b/src/oat/jni/jni_compiler.cc index a9a1bcacfe..9122945df1 100644 --- a/src/oat/jni/jni_compiler.cc +++ b/src/oat/jni/jni_compiler.cc @@ -28,6 +28,7 @@ #include "oat/utils/assembler.h" #include "oat/utils/managed_register.h" #include "oat/utils/arm/managed_register_arm.h" +#include "oat/utils/mips/managed_register_mips.h" #include "oat/utils/x86/managed_register_x86.h" #include "thread.h" #include "UniquePtr.h" diff --git a/src/oat/jni/mips/calling_convention_mips.cc b/src/oat/jni/mips/calling_convention_mips.cc new file mode 100644 index 0000000000..09cc16d120 --- /dev/null +++ b/src/oat/jni/mips/calling_convention_mips.cc @@ -0,0 +1,214 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "calling_convention_mips.h" +#include "logging.h" +#include "oat/utils/mips/managed_register_mips.h" + +namespace art { +namespace mips { + +// Calling convention +ManagedRegister MipsManagedRuntimeCallingConvention::InterproceduralScratchRegister() { + return MipsManagedRegister::FromCoreRegister(T9); +} + +ManagedRegister MipsJniCallingConvention::InterproceduralScratchRegister() { + return MipsManagedRegister::FromCoreRegister(T9); +} + +static ManagedRegister ReturnRegisterForShorty(const char* shorty) { + if (shorty[0] == 'F') { + return MipsManagedRegister::FromFRegister(F0); + } else if (shorty[0] == 'D') { + return MipsManagedRegister::FromDRegister(D0); + } else if (shorty[0] == 'J') { + return MipsManagedRegister::FromRegisterPair(V0_V1); + } else if (shorty[0] == 'V') { + return MipsManagedRegister::NoRegister(); + } else { + return MipsManagedRegister::FromCoreRegister(V0); + } +} + +ManagedRegister MipsManagedRuntimeCallingConvention::ReturnRegister() { + return ReturnRegisterForShorty(GetShorty()); +} + +ManagedRegister MipsJniCallingConvention::ReturnRegister() { + return ReturnRegisterForShorty(GetShorty()); +} + +ManagedRegister MipsJniCallingConvention::IntReturnRegister() { + return MipsManagedRegister::FromCoreRegister(V0); +} + +// Managed runtime calling convention + +ManagedRegister MipsManagedRuntimeCallingConvention::MethodRegister() { + return MipsManagedRegister::FromCoreRegister(V0); +} + +bool MipsManagedRuntimeCallingConvention::IsCurrentParamInRegister() { + return false; // Everything moved to stack on entry. +} + +bool MipsManagedRuntimeCallingConvention::IsCurrentParamOnStack() { + return true; +} + +ManagedRegister MipsManagedRuntimeCallingConvention::CurrentParamRegister() { + LOG(FATAL) << "Should not reach here"; + return ManagedRegister::NoRegister(); +} + +FrameOffset MipsManagedRuntimeCallingConvention::CurrentParamStackOffset() { + CHECK(IsCurrentParamOnStack()); + FrameOffset result = + FrameOffset(displacement_.Int32Value() + // displacement + kPointerSize + // Method* + (itr_slots_ * kPointerSize)); // offset into in args + return result; +} + +const std::vector<ManagedRegister>& MipsManagedRuntimeCallingConvention::EntrySpills() { + // We spill the argument registers on MIPS to free them up for scratch use, we then assume + // all arguments are on the stack. + if (entry_spills_.size() == 0) { + size_t num_spills = NumArgs() + NumLongOrDoubleArgs(); + if (num_spills > 0) { + entry_spills_.push_back(MipsManagedRegister::FromCoreRegister(A1)); + if (num_spills > 1) { + entry_spills_.push_back(MipsManagedRegister::FromCoreRegister(A2)); + if (num_spills > 2) { + entry_spills_.push_back(MipsManagedRegister::FromCoreRegister(A3)); + } + } + } + } + return entry_spills_; +} +// JNI calling convention + +MipsJniCallingConvention::MipsJniCallingConvention(bool is_static, bool is_synchronized, + const char* shorty) + : JniCallingConvention(is_static, is_synchronized, shorty) { + // Compute padding to ensure longs and doubles are not split in AAPCS. Ignore the 'this' jobject + // or jclass for static methods and the JNIEnv. We start at the aligned register r2. + size_t padding = 0; + for (size_t cur_arg = IsStatic() ? 0 : 1, cur_reg = 2; cur_arg < NumArgs(); cur_arg++) { + if (IsParamALongOrDouble(cur_arg)) { + if ((cur_reg & 1) != 0) { + padding += 4; + cur_reg++; // additional bump to ensure alignment + } + cur_reg++; // additional bump to skip extra long word + } + cur_reg++; // bump the iterator for every argument + } + padding_ = padding; + + callee_save_regs_.push_back(MipsManagedRegister::FromCoreRegister(T0)); + callee_save_regs_.push_back(MipsManagedRegister::FromCoreRegister(T1)); + callee_save_regs_.push_back(MipsManagedRegister::FromCoreRegister(T2)); + callee_save_regs_.push_back(MipsManagedRegister::FromCoreRegister(T3)); + callee_save_regs_.push_back(MipsManagedRegister::FromCoreRegister(T4)); + callee_save_regs_.push_back(MipsManagedRegister::FromCoreRegister(T5)); + callee_save_regs_.push_back(MipsManagedRegister::FromCoreRegister(T6)); + callee_save_regs_.push_back(MipsManagedRegister::FromCoreRegister(T7)); + callee_save_regs_.push_back(MipsManagedRegister::FromCoreRegister(T8)); +} + +uint32_t MipsJniCallingConvention::CoreSpillMask() const { + // Compute spill mask to agree with callee saves initialized in the constructor + uint32_t result = 0; + result = 1 << T0 | 1 << T1 | 1 << T2 | 1 << T3 | 1 << T4 | 1 << T5 | 1 << T6 | + 1 << T7 | 1 << T8 | 1 << RA; + return result; +} + +ManagedRegister MipsJniCallingConvention::ReturnScratchRegister() const { + return MipsManagedRegister::FromCoreRegister(AT); +} + +size_t MipsJniCallingConvention::FrameSize() { + // Method*, LR and callee save area size, local reference segment state + size_t frame_data_size = (3 + CalleeSaveRegisters().size()) * kPointerSize; + // References plus 2 words for SIRT header + size_t sirt_size = (ReferenceCount() + 2) * kPointerSize; + // Plus return value spill area size + return RoundUp(frame_data_size + sirt_size + SizeOfReturnValue(), kStackAlignment); +} + +size_t MipsJniCallingConvention::OutArgSize() { + return RoundUp(NumberOfOutgoingStackArgs() * kPointerSize + padding_, + kStackAlignment); +} + +// JniCallingConvention ABI follows AAPCS where longs and doubles must occur +// in even register numbers and stack slots +void MipsJniCallingConvention::Next() { + JniCallingConvention::Next(); + size_t arg_pos = itr_args_ - NumberOfExtraArgumentsForJni(); + if ((itr_args_ >= 2) && + (arg_pos < NumArgs()) && + IsParamALongOrDouble(arg_pos)) { + // itr_slots_ needs to be an even number, according to AAPCS. + if ((itr_slots_ & 0x1u) != 0) { + itr_slots_++; + } + } +} + +bool MipsJniCallingConvention::IsCurrentParamInRegister() { + return itr_slots_ < 4; +} + +bool MipsJniCallingConvention::IsCurrentParamOnStack() { + return !IsCurrentParamInRegister(); +} + +static const Register kJniArgumentRegisters[] = { + A0, A1, A2, A3 +}; +ManagedRegister MipsJniCallingConvention::CurrentParamRegister() { + CHECK_LT(itr_slots_, 4u); + int arg_pos = itr_args_ - NumberOfExtraArgumentsForJni(); + if ((itr_args_ >= 2) && IsParamALongOrDouble(arg_pos)) { + CHECK_EQ(itr_slots_, 2u); + return MipsManagedRegister::FromRegisterPair(A2_A3); + } else { + return + MipsManagedRegister::FromCoreRegister(kJniArgumentRegisters[itr_slots_]); + } +} + +FrameOffset MipsJniCallingConvention::CurrentParamStackOffset() { + CHECK_GE(itr_slots_, 4u); + size_t offset = displacement_.Int32Value() - OutArgSize() + ((itr_slots_ - 4) * kPointerSize); + CHECK_LT(offset, OutArgSize()); + return FrameOffset(offset); +} + +size_t MipsJniCallingConvention::NumberOfOutgoingStackArgs() { + size_t static_args = IsStatic() ? 1 : 0; // count jclass + // regular argument parameters and this + size_t param_args = NumArgs() + NumLongOrDoubleArgs(); + // count JNIEnv* less arguments in registers + return static_args + param_args + 1 - 4; +} +} // namespace mips +} // namespace art diff --git a/src/oat/jni/mips/calling_convention_mips.h b/src/oat/jni/mips/calling_convention_mips.h new file mode 100644 index 0000000000..fd13b61fc2 --- /dev/null +++ b/src/oat/jni/mips/calling_convention_mips.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_SRC_OAT_JNI_MIPS_CALLING_CONVENTION_MIPS_H_ +#define ART_SRC_OAT_JNI_MIPS_CALLING_CONVENTION_MIPS_H_ + +#include "oat/jni/calling_convention.h" + +namespace art { +namespace mips { +class MipsManagedRuntimeCallingConvention : public ManagedRuntimeCallingConvention { + public: + MipsManagedRuntimeCallingConvention(bool is_static, bool is_synchronized, const char* shorty) + : ManagedRuntimeCallingConvention(is_static, is_synchronized, shorty) {} + virtual ~MipsManagedRuntimeCallingConvention() {} + // Calling convention + virtual ManagedRegister ReturnRegister(); + virtual ManagedRegister InterproceduralScratchRegister(); + // Managed runtime calling convention + virtual ManagedRegister MethodRegister(); + virtual bool IsCurrentParamInRegister(); + virtual bool IsCurrentParamOnStack(); + virtual ManagedRegister CurrentParamRegister(); + virtual FrameOffset CurrentParamStackOffset(); + virtual const std::vector<ManagedRegister>& EntrySpills(); + + private: + std::vector<ManagedRegister> entry_spills_; + + DISALLOW_COPY_AND_ASSIGN(MipsManagedRuntimeCallingConvention); +}; + +class MipsJniCallingConvention : public JniCallingConvention { + public: + explicit MipsJniCallingConvention(bool is_static, bool is_synchronized, const char* shorty); + virtual ~MipsJniCallingConvention() {} + // Calling convention + virtual ManagedRegister ReturnRegister(); + virtual ManagedRegister IntReturnRegister(); + virtual ManagedRegister InterproceduralScratchRegister(); + // JNI calling convention + virtual void Next(); // Override default behavior for AAPCS + virtual size_t FrameSize(); + virtual size_t OutArgSize(); + virtual const std::vector<ManagedRegister>& CalleeSaveRegisters() const { + return callee_save_regs_; + } + virtual ManagedRegister ReturnScratchRegister() const; + virtual uint32_t CoreSpillMask() const; + virtual uint32_t FpSpillMask() const { + return 0; // Floats aren't spilled in JNI down call + } + virtual bool IsCurrentParamInRegister(); + virtual bool IsCurrentParamOnStack(); + virtual ManagedRegister CurrentParamRegister(); + virtual FrameOffset CurrentParamStackOffset(); + + protected: + virtual size_t NumberOfOutgoingStackArgs(); + + private: + // TODO: these values aren't unique and can be shared amongst instances + std::vector<ManagedRegister> callee_save_regs_; + + // Padding to ensure longs and doubles are not split in AAPCS + size_t padding_; + + DISALLOW_COPY_AND_ASSIGN(MipsJniCallingConvention); +}; +} // namespace mips +} // namespace art + +#endif // ART_SRC_OAT_JNI_MIPS_CALLING_CONVENTION_MIPS_H_ diff --git a/src/oat/jni/mips/jni_internal_mips.cc b/src/oat/jni/mips/jni_internal_mips.cc new file mode 100644 index 0000000000..0a2ab1da51 --- /dev/null +++ b/src/oat/jni/mips/jni_internal_mips.cc @@ -0,0 +1,172 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include <stdint.h> + +#include <algorithm> + +#include "asm_support.h" +#include "compiled_method.h" +#include "compiler.h" +#include "oat/utils/mips/assembler_mips.h" +#include "oat/utils/assembler.h" +#include "object.h" + +namespace art { +namespace mips { +// Creates a function which invokes a managed method with an array of +// arguments. +// +// At the time of call, the environment looks something like this: +// +// A0 = method pointer +// A1 = receiver pointer or NULL for static methods +// A2 = (managed) thread pointer +// A3 = argument array or NULL for no argument methods +// [SP] = JValue* result or NULL for void returns +// +// As the JNI call has already transitioned the thread into the +// "running" state the remaining responsibilities of this routine are +// to save the native register value and restore the managed thread +// register and transfer arguments from the array into register and on +// the stack, if needed. On return, the thread register must be +// shuffled and the return value must be store into the result JValue. +CompiledInvokeStub* CreateInvokeStub(bool is_static, const char* shorty, uint32_t shorty_len) { + UniquePtr<MipsAssembler> assembler(down_cast<MipsAssembler*>(Assembler::Create(kMips))); +#define __ assembler-> + size_t num_arg_array_bytes = NumArgArrayBytes(shorty, shorty_len); + // Size of frame = spill of R4,R9/LR + Method* + possible receiver + arg array size + // Note, space is left in the frame to flush arguments in registers back to out locations. + size_t unpadded_frame_size = (4 * kPointerSize) + + (is_static ? 0 : kPointerSize) + + num_arg_array_bytes; + size_t frame_size = RoundUp(unpadded_frame_size, kStackAlignment); + + // Setup frame and spill S0 (rSUSPEND), S1 (rSELF), and RA + __ AddConstant(SP, SP, -frame_size); + __ StoreToOffset(kStoreWord, RA, SP, frame_size - 4); + __ StoreToOffset(kStoreWord, S1, SP, frame_size - 8); + __ StoreToOffset(kStoreWord, S0, SP, frame_size - 12); + + // Move the managed thread pointer into S1. + __ Move(S1, A2); + + // Reset S0 to suspend check interval + __ LoadImmediate(S0, SUSPEND_CHECK_INTERVAL); + + // Can either get 3 or 2 arguments into registers + size_t reg_bytes = (is_static ? 3 : 2) * kPointerSize; + if (num_arg_array_bytes <= reg_bytes) { + reg_bytes = num_arg_array_bytes; + } + + // Copy values onto the stack. + size_t src_offset = 0; + size_t dst_offset = (is_static ? 1 : 2) * kPointerSize; + for (size_t i = 1; i < shorty_len; ++i) { + switch (shorty[i]) { + case 'D': + case 'J': + // Move both pointers 64 bits. + __ LoadFromOffset(kLoadWord, T9, A3, src_offset); + src_offset += kPointerSize; + __ StoreToOffset(kStoreWord, T9, SP, dst_offset); + dst_offset += kPointerSize; + + __ LoadFromOffset(kLoadWord, T9, A3, src_offset); + src_offset += kPointerSize; + __ StoreToOffset(kStoreWord, T9, SP, dst_offset); + dst_offset += kPointerSize; + break; + default: + // Move the source pointer sizeof(JValue) and the destination pointer 32 bits. + __ LoadFromOffset(kLoadWord, T9, A3, src_offset); + src_offset += sizeof(JValue); + __ StoreToOffset(kStoreWord, T9, SP, dst_offset); + dst_offset += kPointerSize; + break; + } + } + + // Move all the register arguments into place. + dst_offset = (is_static ? 1 : 2) * kPointerSize; + if (is_static) { + if (reg_bytes > 0 && num_arg_array_bytes > 0) { + __ LoadFromOffset(kLoadWord, A1, SP, dst_offset + 0); + if (reg_bytes > 4 && num_arg_array_bytes > 4) { + __ LoadFromOffset(kLoadWord, A2, SP, dst_offset + 4); + if (reg_bytes > 8 && num_arg_array_bytes > 8) { + __ LoadFromOffset(kLoadWord, A3, SP, dst_offset + 8); + } + } + } + } else { + if (reg_bytes > 0 && num_arg_array_bytes > 0) { + __ LoadFromOffset(kLoadWord, A2, SP, dst_offset + 0); + if (reg_bytes > 4 && num_arg_array_bytes > 4) { + __ LoadFromOffset(kLoadWord, A3, SP, dst_offset + 4); + } + } + } + + // Load the code pointer we are about to call. + __ LoadFromOffset(kLoadWord, T9, A0, Method::GetCodeOffset().Int32Value()); + + // Do the call. + __ Jalr(T9); + + // If the method returns a value, store it to the result pointer. + if (shorty[0] != 'V') { + // Load the result JValue pointer of the stub caller's out args. + __ LoadFromOffset(kLoadWord, T9, SP, frame_size); + switch (shorty[0]) { + case 'D': + __ StoreDToOffset(D0, T9, 0); + break; + case 'F': + __ StoreFToOffset(F0, T9, 0); + break; + case 'J': + __ StoreToOffset(kStoreWord, V0, T9, 0); + __ StoreToOffset(kStoreWord, V1, T9, 4); + break; + default: + __ StoreToOffset(kStoreWord, V0, T9, 0); + } + } + + // Restore frame and spill regs + __ LoadFromOffset(kLoadWord, S0, SP, frame_size - 12); + __ LoadFromOffset(kLoadWord, S1, SP, frame_size - 8); + __ LoadFromOffset(kLoadWord, RA, SP, frame_size - 4); + __ AddConstant(SP, SP, frame_size); + + __ Jr(RA); + + // TODO: store native_entry in the stub table + std::vector<uint8_t> code(assembler->CodeSize()); + MemoryRegion region(&code[0], code.size()); + assembler->FinalizeInstructions(region); + return new CompiledInvokeStub(kMips, code); +#undef __ +} +} // namespace mips +} // namespace art + +extern "C" art::CompiledInvokeStub* ArtCreateInvokeStub(art::Compiler& /*compiler*/, bool is_static, + const char* shorty, uint32_t shorty_len) { + return art::mips::CreateInvokeStub(is_static, shorty, shorty_len); +} diff --git a/src/oat/runtime/context.cc b/src/oat/runtime/context.cc index 30733775ed..729f044a2f 100644 --- a/src/oat/runtime/context.cc +++ b/src/oat/runtime/context.cc @@ -18,7 +18,9 @@ #if defined(__arm__) #include "arm/context_arm.h" -#else +#elif defined(__mips__) +#include "mips/context_mips.h" +#elif defined(__i386__) #include "x86/context_x86.h" #endif @@ -27,8 +29,12 @@ namespace art { Context* Context::Create() { #if defined(__arm__) return new arm::ArmContext(); -#else +#elif defined(__mips__) + return new mips::MipsContext(); +#elif defined(__i386__) return new x86::X86Context(); +#else + UNIMPLEMENTED(WARNING); #endif } diff --git a/src/oat/runtime/mips/context_mips.cc b/src/oat/runtime/mips/context_mips.cc new file mode 100644 index 0000000000..ded90854c6 --- /dev/null +++ b/src/oat/runtime/mips/context_mips.cc @@ -0,0 +1,82 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "context_mips.h" + +#include "object.h" + +namespace art { +namespace mips { + +MipsContext::MipsContext() { +#ifndef NDEBUG + // Initialize registers with easy to spot debug values. + for (int i = 0; i < 32; i++) { + gprs_[i] = kBadGprBase + i; + } + for (int i = 0; i < 32; i++) { + fprs_[i] = kBadGprBase + i; + } + pc_ = 0xEBAD601F; +#endif +} + +void MipsContext::FillCalleeSaves(const StackVisitor& fr) { + Method* method = fr.GetMethod(); + uint32_t core_spills = method->GetCoreSpillMask(); + uint32_t fp_core_spills = method->GetFpSpillMask(); + size_t spill_count = __builtin_popcount(core_spills); + size_t fp_spill_count = __builtin_popcount(fp_core_spills); + size_t frame_size = method->GetFrameSizeInBytes(); + if (spill_count > 0) { + // Lowest number spill is furthest away, walk registers and fill into context. + int j = 1; + for (int i = 0; i < 32; i++) { + if (((core_spills >> i) & 1) != 0) { + gprs_[i] = fr.LoadCalleeSave(spill_count - j, frame_size); + j++; + } + } + } + if (fp_spill_count > 0) { + // Lowest number spill is furthest away, walk registers and fill into context. + int j = 1; + for (int i = 0; i < 32; i++) { + if (((fp_core_spills >> i) & 1) != 0) { + fprs_[i] = fr.LoadCalleeSave(spill_count +fp_spill_count - j, frame_size); + j++; + } + } + } +} + +void MipsContext::SmashCallerSaves() { + gprs_[V0] = 0; // This needs to be 0 because we want a null/zero return value. + gprs_[V1] = 0; // This needs to be 0 because we want a null/zero return value. + gprs_[A1] = kBadGprBase + A1; + gprs_[A2] = kBadGprBase + A2; + gprs_[A3] = kBadGprBase + A3; + gprs_[RA] = kBadGprBase + RA; +} + +extern "C" void art_do_long_jump(uint32_t*, uint32_t*); + +void MipsContext::DoLongJump() { + art_do_long_jump(&gprs_[ZERO], &fprs_[F0]); +} + +} // namespace mips +} // namespace art diff --git a/src/oat/runtime/mips/context_mips.h b/src/oat/runtime/mips/context_mips.h new file mode 100644 index 0000000000..da4fc6acc2 --- /dev/null +++ b/src/oat/runtime/mips/context_mips.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_SRC_OAT_RUNTIME_MIPS_CONTEXT_MIPS_H_ +#define ART_SRC_OAT_RUNTIME_MIPS_CONTEXT_MIPS_H_ + +#include "constants_mips.h" +#include "oat/runtime/context.h" + +namespace art { +namespace mips { + +class MipsContext : public Context { + public: + MipsContext(); + virtual ~MipsContext() {} + + // No callee saves on mips + virtual void FillCalleeSaves(const StackVisitor& fr); + + virtual void SetSP(uintptr_t new_sp) { + gprs_[SP] = new_sp; + } + + virtual void SetPC(uintptr_t new_pc) { + pc_ = new_pc; + } + + virtual uintptr_t GetGPR(uint32_t reg) { + CHECK_GE(reg, 0u); + CHECK_LT(reg, 32u); + return gprs_[reg]; + } + + virtual void SmashCallerSaves(); + virtual void DoLongJump(); + + private: + uintptr_t gprs_[32]; + uint32_t fprs_[32]; + uintptr_t pc_; +}; +} // namespace mips +} // namespace art + +#endif // ART_SRC_OAT_RUNTIME_MIPS_CONTEXT_MIPS_H_ diff --git a/src/oat/runtime/mips/oat_support_entrypoints_mips.cc b/src/oat/runtime/mips/oat_support_entrypoints_mips.cc index c131be4570..f9188cc565 100644 --- a/src/oat/runtime/mips/oat_support_entrypoints_mips.cc +++ b/src/oat/runtime/mips/oat_support_entrypoints_mips.cc @@ -28,7 +28,7 @@ extern "C" void* art_check_and_alloc_array_from_code(uint32_t, void*, int32_t); extern "C" void* art_check_and_alloc_array_from_code_with_access_check(uint32_t, void*, int32_t); // Cast entrypoints. -extern uint32_t IsAssignableFromCode(const Class* klass, const Class* ref_class); +extern "C" uint32_t artIsAssignableFromCode(const Class* klass, const Class* ref_class); extern "C" void art_can_put_array_element_from_code(void*, void*); extern "C" void art_check_cast_from_code(void*, void*); @@ -60,8 +60,17 @@ extern "C" void* art_get_obj_static_from_code(uint32_t); extern "C" void art_handle_fill_data_from_code(void*, void*); // JNI entrypoints. -extern Object* DecodeJObjectInThread(Thread* thread, jobject obj); extern void* FindNativeMethod(Thread* thread); +extern uint32_t JniMethodStart(Thread* self); +extern uint32_t JniMethodStartSynchronized(jobject to_lock, Thread* self); +extern void JniMethodEnd(uint32_t saved_local_ref_cookie, Thread* self); +extern void JniMethodEndSynchronized(uint32_t saved_local_ref_cookie, jobject locked, + Thread* self); +extern Object* JniMethodEndWithReference(jobject result, uint32_t saved_local_ref_cookie, + Thread* self); +extern Object* JniMethodEndWithReferenceSynchronized(jobject result, + uint32_t saved_local_ref_cookie, + jobject locked, Thread* self); // Lock entrypoints. extern "C" void art_lock_object_from_code(void*); @@ -149,7 +158,7 @@ void InitEntryPoints(EntryPoints* points) { points->pCheckAndAllocArrayFromCodeWithAccessCheck = art_check_and_alloc_array_from_code_with_access_check; // Cast - points->pInstanceofNonTrivialFromCode = IsAssignableFromCode; + points->pInstanceofNonTrivialFromCode = artIsAssignableFromCode; points->pCanPutArrayElementFromCode = art_can_put_array_element_from_code; points->pCheckCastFromCode = art_check_cast_from_code; @@ -181,8 +190,13 @@ void InitEntryPoints(EntryPoints* points) { points->pHandleFillArrayDataFromCode = art_handle_fill_data_from_code; // JNI - points->pDecodeJObjectInThread = DecodeJObjectInThread; points->pFindNativeMethod = FindNativeMethod; + points->pJniMethodStart = JniMethodStart; + points->pJniMethodStartSynchronized = JniMethodStartSynchronized; + points->pJniMethodEnd = JniMethodEnd; + points->pJniMethodEndSynchronized = JniMethodEndSynchronized; + points->pJniMethodEndWithReference = JniMethodEndWithReference; + points->pJniMethodEndWithReferenceSynchronized = JniMethodEndWithReferenceSynchronized; // Locks points->pLockObjectFromCode = art_lock_object_from_code; @@ -210,7 +224,7 @@ void InitEntryPoints(EntryPoints* points) { points->pI2f = __floatsisf; points->pL2f = __floatdisf; points->pD2iz = __fixdfsi; - points->pF2iz = __fixsfi; + points->pF2iz = __fixsfsi; points->pIdivmod = NULL; points->pD2l = art_d2l; points->pF2l = art_f2l; @@ -255,7 +269,7 @@ void ChangeDebuggerEntryPoint(EntryPoints* points, bool enabled) { points->pUpdateDebuggerFromCode = (enabled ? art_update_debugger : NULL); } -bool IsTraceExitPc(uintptr_t pc) { +bool IsTraceExitPc(uintptr_t) { UNIMPLEMENTED(FATAL); return false; } diff --git a/src/oat/runtime/mips/runtime_support_mips.S b/src/oat/runtime/mips/runtime_support_mips.S index d4e87c0f2e..3ffe059e25 100644 --- a/src/oat/runtime/mips/runtime_support_mips.S +++ b/src/oat/runtime/mips/runtime_support_mips.S @@ -31,80 +31,80 @@ /* * Macro that sets up the callee save frame to conform with * Runtime::CreateCalleeSaveMethod(kSaveAll) - * callee-save: s0-s8 + ra, 10 total + 2 words + * callee-save: $s0-$s8 + $ra, 10 total + 2 words */ .macro SETUP_SAVE_ALL_CALLEE_SAVE_FRAME - addiu sp, sp, 48 - sw ra, 44(sp) - sw s8, 40(sp) - sw s7, 36(sp) - sw s6, 32(sp) - sw s5, 28(sp) - sw s4, 24(sp) - sw s3, 20(sp) - sw s2, 16(sp) - sw s1, 12(sp) - sw s0, 8(sp) - @ 2 open words, bottom will hold Method* + addiu $sp, $sp, 48 + sw $ra, 44($sp) + sw $s8, 40($sp) + sw $s7, 36($sp) + sw $s6, 32($sp) + sw $s5, 28($sp) + sw $s4, 24($sp) + sw $s3, 20($sp) + sw $s2, 16($sp) + sw $s1, 12($sp) + sw $s0, 8($sp) + # 2 open words, bottom will hold Method* .endm /* * Macro that sets up the callee save frame to conform with * Runtime::CreateCalleeSaveMethod(kRefsOnly). Restoration assumes non-moving GC. * Does not include rSUSPEND or rSELF - * callee-save: s2-s8 + ra, 8 total + 4 words + * callee-save: $s2-$s8 + $ra, 8 total + 4 words */ .macro SETUP_REF_ONLY_CALLEE_SAVE_FRAME - addiu sp, sp, 48 - sw ra, 44(sp) - sw s8, 40(sp) - sw s7, 36(sp) - sw s6, 32(sp) - sw s5, 28(sp) - sw s4, 24(sp) - sw s3, 20(sp) - sw s2, 16(sp) - @ 4 open words, bottom will hold Method* + addiu $sp, $sp, 48 + sw $ra, 44($sp) + sw $s8, 40($sp) + sw $s7, 36($sp) + sw $s6, 32($sp) + sw $s5, 28($sp) + sw $s4, 24($sp) + sw $s3, 20($sp) + sw $s2, 16($sp) + # 4 open words, bottom will hold Method* .endm .macro RESTORE_REF_ONLY_CALLEE_SAVE_FRAME - lw ra, 44(sp) - addiu sp, sp, 48 + lw $ra, 44($sp) + addiu $sp, $sp, 48 .endm .macro RESTORE_REF_ONLY_CALLEE_SAVE_FRAME_AND_RETURN - lw ra, 44(sp) - jr ra - addiu sp, sp, 48 + lw $ra, 44($sp) + jr $ra + addiu $sp, $sp, 48 .endm /* * Macro that sets up the callee save frame to conform with * Runtime::CreateCalleeSaveMethod(kRefsAndArgs). Restoration assumes non-moving GC. - * a1-a3, s2-s8, ra, 11 total + 1 + * $a1-$a3, $s2-$s8, $ra, 11 total + 1 */ .macro SETUP_REF_AND_ARGS_CALLEE_SAVE_FRAME - addiu sp, sp, 48 - sw ra, 44(sp) - sw s8, 40(sp) - sw s7, 36(sp) - sw s6, 32(sp) - sw s5, 28(sp) - sw s4, 24(sp) - sw s3, 20(sp) - sw s2, 16(sp) - sw a3, 12(sp) - sw a2, 8(sp) - sw a1, 4(sp) - @ 1 open word, bottom will hold Method* + addiu $sp, $sp, 48 + sw $ra, 44($sp) + sw $s8, 40($sp) + sw $s7, 36($sp) + sw $s6, 32($sp) + sw $s5, 28($sp) + sw $s4, 24($sp) + sw $s3, 20($sp) + sw $s2, 16($sp) + sw $a3, 12($sp) + sw $a2, 8($sp) + sw $a1, 4($sp) + # 1 open word, bottom will hold Method* .endm .macro RESTORE_REF_AND_ARGS_CALLEE_SAVE_FRAME - lw ra, 44(sp) @ restore ra - lw a1, 4(sp) @ restore non-callee save a1 - lw a2, 8(sp) @ restore non-callee save a2 - lw a3, 12(sp) @ restore non-callee save a3 - addiu sp, sp, 48 @ strip frame + lw $ra, 44($sp) # restore $ra + lw $a1, 4($sp) # restore non-callee save $a1 + lw $a2, 8($sp) # restore non-callee save $a2 + lw $a3, 12($sp) # restore non-callee save $a3 + addiu $sp, $sp, 48 # strip frame .endm /* @@ -112,18 +112,18 @@ * exception is Thread::Current()->exception_ */ .macro DELIVER_PENDING_EXCEPTION - SETUP_SAVE_ALL_CALLEE_SAVE_FRAME @ save callee saves for throw - move a0, rSELF @ pass Thread::Current - b artDeliverPendingExceptionFromCode @ artDeliverPendingExceptionFromCode(Thread*, SP) - move a1, sp @ pass SP + SETUP_SAVE_ALL_CALLEE_SAVE_FRAME # save callee saves for throw + move $a0, rSELF # pass Thread::Current + jal artDeliverPendingExceptionFromCode # artDeliverPendingExceptionFromCode(Thread*, $sp) + move $a1, $sp # pass $sp .endm .macro RETURN_IF_NO_EXCEPTION - lw t0, THREAD_EXCEPTION_OFFSET(rSELF) @ load Thread::Current()->exception_ + lw $t0, THREAD_EXCEPTION_OFFSET(rSELF) # load Thread::Current()->exception_ RESTORE_REF_ONLY_CALLEE_SAVE_FRAME - bnez t0, 1f @ success if no exception is pending + bnez $t0, 1f # success if no exception is pending nop - jr ra + jr $ra nop 1: DELIVER_PENDING_EXCEPTION @@ -131,9 +131,9 @@ .macro RETURN_IF_ZERO RESTORE_REF_ONLY_CALLEE_SAVE_FRAME - bnez v0, 1f @ success? + bnez $v0, 1f # success? nop - jr ra @ return on success + jr $ra # return on success nop 1: DELIVER_PENDING_EXCEPTION @@ -141,9 +141,9 @@ .macro RETURN_IF_NONZERO RESTORE_REF_ONLY_CALLEE_SAVE_FRAME - beqz v0, 1f @ success? + beqz $v0, 1f # success? nop - jr ra @ return on success + jr $ra # return on success nop 1: DELIVER_PENDING_EXCEPTION @@ -152,93 +152,93 @@ .global art_update_debugger .extern artUpdateDebuggerFromCode /* - * On entry, a0 and a1 must be preserved, a2 is dex PC + * On entry, $a0 and $a1 must be preserved, $a2 is dex PC */ ALIGN_FUNCTION_ENTRY art_update_debugger: - move a3, a0 @ stash away a0 so that it's saved as if it were an argument + move $a3, $a0 # stash away $a0 so that it's saved as if it were an argument SETUP_REF_AND_ARGS_CALLEE_SAVE_FRAME - move a0, a2 @ arg0 is dex PC - move a1, rSELF @ arg1 is Thread* - move a2, sp @ arg2 is sp - jal artUpdateDebuggerFromCode @ artUpdateDebuggerFromCode(int32_t, Thread*, Method**) + move $a0, $a2 # arg0 is dex PC + move $a1, rSELF # arg1 is Thread* + move $a2, $sp # arg2 is $sp + jal artUpdateDebuggerFromCode # artUpdateDebuggerFromCode(int32_t, Thread*, Method**) RESTORE_REF_AND_ARGS_CALLEE_SAVE_FRAME - jr ra - move a0, a3 @ restore original a0 + jr $ra + move $a0, $a3 # restore original $a0 .global art_do_long_jump /* - * On entry a0 is uint32_t* gprs_ and a1 is uint32_t* fprs_ + * On entry $a0 is uint32_t* gprs_ and $a1 is uint32_t* fprs_ * FIXME: just guessing about the shape of the jmpbuf. Where will pc be? */ ALIGN_FUNCTION_ENTRY art_do_long_jump: - l.s f0, 0(a1) - l.s f1, 4(a1) - l.s f2, 8(a1) - l.s f3, 12(a1) - l.s f4, 16(a1) - l.s f5, 20(a1) - l.s f6, 24(a1) - l.s f7, 28(a1) - l.s f8, 32(a1) - l.s f9, 36(a1) - l.s f10, 40(a1) - l.s f11, 44(a1) - l.s f12, 48(a1) - l.s f13, 52(a1) - l.s f14, 56(a1) - l.s f15, 60(a1) - l.s f16, 64(a1) - l.s f17, 68(a1) - l.s f18, 72(a1) - l.s f19, 76(a1) - l.s f20, 80(a1) - l.s f21, 84(a1) - l.s f22, 88(a1) - l.s f23, 92(a1) - l.s f24, 96(a1) - l.s f25, 100(a1) - l.s f26, 104(a1) - l.s f27, 108(a1) - l.s f28, 112(a1) - l.s f29, 116(a1) - l.s f30, 120(a1) - l.s f31, 124(a1) - lw at, 4(a0) - lw v0, 8(a0) - lw v1, 12(a0) - lw a1, 20(a0) - lw a2, 24(a0) - lw a3, 28(a0) - lw t0, 32(a0) - lw t1, 36(a0) - lw t2, 40(a0) - lw t3, 44(a0) - lw t4, 48(a0) - lw t5, 52(a0) - lw t6, 56(a0) - lw t7, 60(a0) - lw s0, 64(a0) - lw s1, 68(a0) - lw s2, 72(a0) - lw s3, 76(a0) - lw s4, 80(a0) - lw s5, 84(a0) - lw s6, 88(a0) - lw s7, 92(a0) - lw t8, 96(a0) - lw t9, 100(a0) - lw k0, 104(a0) - lw k1, 108(a0) - lw gp, 112(a0) - lw sp, 116(a0) - lw fp, 120(a0) - lw ra, 124(a0) - lw a0, 16(a0) - move v0, rzero @ clear result registers r0 and r1 - jr ra @ do long jump - move v1, rzero + l.s $f0, 0($a1) + l.s $f1, 4($a1) + l.s $f2, 8($a1) + l.s $f3, 12($a1) + l.s $f4, 16($a1) + l.s $f5, 20($a1) + l.s $f6, 24($a1) + l.s $f7, 28($a1) + l.s $f8, 32($a1) + l.s $f9, 36($a1) + l.s $f10, 40($a1) + l.s $f11, 44($a1) + l.s $f12, 48($a1) + l.s $f13, 52($a1) + l.s $f14, 56($a1) + l.s $f15, 60($a1) + l.s $f16, 64($a1) + l.s $f17, 68($a1) + l.s $f18, 72($a1) + l.s $f19, 76($a1) + l.s $f20, 80($a1) + l.s $f21, 84($a1) + l.s $f22, 88($a1) + l.s $f23, 92($a1) + l.s $f24, 96($a1) + l.s $f25, 100($a1) + l.s $f26, 104($a1) + l.s $f27, 108($a1) + l.s $f28, 112($a1) + l.s $f29, 116($a1) + l.s $f30, 120($a1) + l.s $f31, 124($a1) + lw $at, 4($a0) + lw $v0, 8($a0) + lw $v1, 12($a0) + lw $a1, 20($a0) + lw $a2, 24($a0) + lw $a3, 28($a0) + lw $t0, 32($a0) + lw $t1, 36($a0) + lw $t2, 40($a0) + lw $t3, 44($a0) + lw $t4, 48($a0) + lw $t5, 52($a0) + lw $t6, 56($a0) + lw $t7, 60($a0) + lw $s0, 64($a0) + lw $s1, 68($a0) + lw $s2, 72($a0) + lw $s3, 76($a0) + lw $s4, 80($a0) + lw $s5, 84($a0) + lw $s6, 88($a0) + lw $s7, 92($a0) + lw $t8, 96($a0) + lw $t9, 100($a0) + lw $k0, 104($a0) + lw $k1, 108($a0) + lw $gp, 112($a0) + lw $sp, 116($a0) + lw $fp, 120($a0) + lw $ra, 124($a0) + lw $a0, 16($a0) + move $v0, $zero # clear result registers r0 and r1 + jr $ra # do long jump + move $v1, $zero .global art_deliver_exception_from_code /* @@ -249,9 +249,9 @@ art_do_long_jump: ALIGN_FUNCTION_ENTRY art_deliver_exception_from_code: SETUP_SAVE_ALL_CALLEE_SAVE_FRAME - move a1, rSELF @ pass Thread::Current - b artDeliverExceptionFromCode @ artDeliverExceptionFromCode(Throwable*, Thread*, SP) - move a2, sp @ pass SP + move $a1, rSELF # pass Thread::Current + jal artDeliverExceptionFromCode # artDeliverExceptionFromCode(Throwable*, Thread*, $sp) + move $a2, $sp # pass $sp .global art_throw_null_pointer_exception_from_code .extern artThrowNullPointerExceptionFromCode @@ -261,9 +261,9 @@ art_deliver_exception_from_code: ALIGN_FUNCTION_ENTRY art_throw_null_pointer_exception_from_code: SETUP_SAVE_ALL_CALLEE_SAVE_FRAME - move a0, rSELF @ pass Thread::Current - b artThrowNullPointerExceptionFromCode @ artThrowNullPointerExceptionFromCode(Thread*, SP) - move a1, sp @ pass SP + move $a0, rSELF # pass Thread::Current + jal artThrowNullPointerExceptionFromCode # artThrowNullPointerExceptionFromCode(Thread*, $sp) + move $a1, $sp # pass $sp .global art_throw_div_zero_from_code .extern artThrowDivZeroFromCode @@ -273,9 +273,9 @@ art_throw_null_pointer_exception_from_code: ALIGN_FUNCTION_ENTRY art_throw_div_zero_from_code: SETUP_SAVE_ALL_CALLEE_SAVE_FRAME - move a0, rSELF @ pass Thread::Current - b artThrowDivZeroFromCode @ artThrowDivZeroFromCode(Thread*, SP) - move a1, sp @ pass SP + move $a0, rSELF # pass Thread::Current + jal artThrowDivZeroFromCode # artThrowDivZeroFromCode(Thread*, $sp) + move $a1, $sp # pass $sp .global art_throw_array_bounds_from_code .extern artThrowArrayBoundsFromCode @@ -285,9 +285,9 @@ art_throw_div_zero_from_code: ALIGN_FUNCTION_ENTRY art_throw_array_bounds_from_code: SETUP_SAVE_ALL_CALLEE_SAVE_FRAME - move a2, rSELF @ pass Thread::Current - b artThrowArrayBoundsFromCode @ artThrowArrayBoundsFromCode(index, limit, Thread*, SP) - move a3, sp @ pass SP + move $a2, rSELF # pass Thread::Current + jal artThrowArrayBoundsFromCode # artThrowArrayBoundsFromCode(index, limit, Thread*, $sp) + move $a3, $sp # pass $sp .global art_throw_stack_overflow_from_code .extern artThrowStackOverflowFromCode @@ -297,21 +297,9 @@ art_throw_array_bounds_from_code: ALIGN_FUNCTION_ENTRY art_throw_stack_overflow_from_code: SETUP_SAVE_ALL_CALLEE_SAVE_FRAME - move a1, rSELF @ pass Thread::Current - b artThrowStackOverflowFromCode @ artThrowStackOverflowFromCode(method, Thread*, SP) - move a2, sp @ pass SP - - .global art_throw_neg_array_size_from_code - .extern artThrowNegArraySizeFromCode - /* - * Called by managed code to create and deliver a NegativeArraySizeException. - */ - ALIGN_FUNCTION_ENTRY -art_throw_neg_array_size_from_code: - SETUP_SAVE_ALL_CALLEE_SAVE_FRAME - move a1, rSELF @ pass Thread::Current - b artThrowNegArraySizeFromCode @ artThrowNegArraySizeFromCode(size, Thread*, SP) - move a2, sp @ pass SP + move $a1, rSELF # pass Thread::Current + jal artThrowStackOverflowFromCode # artThrowStackOverflowFromCode(method, Thread*, $sp) + move $a2, $sp # pass $sp .global art_throw_no_such_method_from_code .extern artThrowNoSuchMethodFromCode @@ -321,9 +309,9 @@ art_throw_neg_array_size_from_code: ALIGN_FUNCTION_ENTRY art_throw_no_such_method_from_code: SETUP_SAVE_ALL_CALLEE_SAVE_FRAME - move a1, rSELF @ pass Thread::Current - b artThrowNoSuchMethodFromCode @ artThrowNoSuchMethodFromCode(method_idx, Thread*, SP) - move a2, sp @ pass SP + move $a1, rSELF # pass Thread::Current + jal artThrowNoSuchMethodFromCode # artThrowNoSuchMethodFromCode(method_idx, Thread*, $sp) + move $a2, $sp # pass $sp .global art_throw_verification_error_from_code .extern artThrowVerificationErrorFromCode @@ -333,19 +321,19 @@ art_throw_no_such_method_from_code: ALIGN_FUNCTION_ENTRY art_throw_verification_error_from_code: SETUP_SAVE_ALL_CALLEE_SAVE_FRAME - move a2, rSELF @ pass Thread::Current - b artThrowVerificationErrorFromCode @ artThrowVerificationErrorFromCode(kind, ref, Thread*, SP) - move a3, sp @ pass SP + move $a2, rSELF # pass Thread::Current + jal artThrowVerificationErrorFromCode # artThrowVerificationErrorFromCode(kind, ref, Thread*, $sp) + move $a3, $sp # pass $sp /* * All generated callsites for interface invokes and invocation slow paths will load arguments - * as usual - except instead of loading arg0/a0 with the target Method*, arg0/a0 will contain + * as usual - except instead of loading arg0/$a0 with the target Method*, arg0/$a0 will contain * the method_idx. This wrapper will save arg1-arg3, load the caller's Method*, align the * stack and call the appropriate C helper. - * NOTE: "this" is first visable argument of the target, and so can be found in arg1/a1. + * NOTE: "this" is first visable argument of the target, and so can be found in arg1/$a1. * - * The helper will attempt to locate the target and return a 64-bit result in v0/v1 consisting - * of the target Method* in v0 and method->code_ in v1. + * The helper will attempt to locate the target and return a 64-bit result in $v0/$v1 consisting + * of the target Method* in $v0 and method->code_ in $v1. * * If unsuccessful, the helper will return NULL/NULL. There will bea pending exception in the * thread and we branch to another stub to deliver it. @@ -357,16 +345,16 @@ art_throw_verification_error_from_code: .global \c_name .extern \cxx_name \c_name: - SETUP_REF_AND_ARGS_CALLEE_SAVE_FRAME @ save callee saves in case allocation triggers GC - lw a2, 48(sp) @ pass caller Method* - move a3, rSELF @ pass Thread::Current - sw sp, 0(sp) @ pass SP - jal \cxx_name @ (method_idx, this, caller, Thread*, SP) - move t0, v1 @ save v0->code_ + SETUP_REF_AND_ARGS_CALLEE_SAVE_FRAME # save callee saves in case allocation triggers GC + lw $a2, 48($sp) # pass caller Method* + move $a3, rSELF # pass Thread::Current + sw $sp, 0($sp) # pass $sp + jal \cxx_name # (method_idx, this, caller, Thread*, $sp) + move $t0, $v1 # save $v0->code_ RESTORE_REF_AND_ARGS_CALLEE_SAVE_FRAME - bnez v0, 1f + bnez $v0, 1f nop - jr t0 + jr $t0 nop 1: DELIVER_PENDING_EXCEPTION @@ -387,24 +375,24 @@ INVOKE_TRAMPOLINE art_invoke_virtual_trampoline_with_access_check, artInvokeVirt */ ALIGN_FUNCTION_ENTRY art_work_around_app_jni_bugs: - @ save registers that may contain arguments and LR that will be crushed by a call - addiu sp, sp, -32 - sw a0, 28(sp) - sw a1, 24(sp) - sw a2, 20(sp) - sw a3, 16(sp) - sw ra, 12(sp) - move a0, rSELF @ pass Thread::Current - jal artWorkAroundAppJniBugs @ (Thread*, SP) - move a1, sp @ pass SP - move t0, v0 @ save target address - lw a0, 28(sp) - lw a1, 24(sp) - lw a2, 20(sp) - lw a3, 16(sp) - lw ra, 12(sp) - jr t0 @ tail call into JNI routine - addiu sp, sp, 32 + # save registers that may contain arguments and LR that will be crushed by a call + addiu $sp, $sp, -32 + sw $a0, 28($sp) + sw $a1, 24($sp) + sw $a2, 20($sp) + sw $a3, 16($sp) + sw $ra, 12($sp) + move $a0, rSELF # pass Thread::Current + jal artWorkAroundAppJniBugs # (Thread*, $sp) + move $a1, $sp # pass $sp + move $t0, $v0 # save target address + lw $a0, 28($sp) + lw $a1, 24($sp) + lw $a2, 20($sp) + lw $a3, 16($sp) + lw $ra, 12($sp) + jr $t0 # tail call into JNI routine + addiu $sp, $sp, 32 .global art_handle_fill_data_from_code .extern artHandleFillArrayDataFromCode @@ -414,14 +402,14 @@ art_work_around_app_jni_bugs: */ ALIGN_FUNCTION_ENTRY art_handle_fill_data_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case exception allocation triggers GC - move a2, rSELF @ pass Thread::Current - jal artHandleFillArrayDataFromCode @ (Array*, const DexFile::Payload*, Thread*, SP) - move a3, sp @ pass SP + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case exception allocation triggers GC + move $a2, rSELF # pass Thread::Current + jal artHandleFillArrayDataFromCode # (Array*, const DexFile::Payload*, Thread*, $sp) + move $a3, $sp # pass $sp RESTORE_REF_ONLY_CALLEE_SAVE_FRAME - bnez v0, 1f @ success? + bnez $v0, 1f # success? nop - jr ra @ return on success + jr $ra # return on success nop 1: DELIVER_PENDING_EXCEPTION @@ -433,10 +421,10 @@ art_handle_fill_data_from_code: */ ALIGN_FUNCTION_ENTRY art_lock_object_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case we block - move a1, rSELF @ pass Thread::Current - jal artLockObjectFromCode @ (Object* obj, Thread*, SP) - move a2, sp @ pass SP + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case we block + move $a1, rSELF # pass Thread::Current + jal artLockObjectFromCode # (Object* obj, Thread*, $sp) + move $a2, $sp # pass $sp RESTORE_REF_ONLY_CALLEE_SAVE_FRAME_AND_RETURN .global art_unlock_object_from_code @@ -446,10 +434,10 @@ art_lock_object_from_code: */ ALIGN_FUNCTION_ENTRY art_unlock_object_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case exception allocation triggers GC - move a1, rSELF @ pass Thread::Current - jal artUnlockObjectFromCode @ (Object* obj, Thread*, SP) - move a2, sp @ pass SP + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case exception allocation triggers GC + move $a1, rSELF # pass Thread::Current + jal artUnlockObjectFromCode # (Object* obj, Thread*, $sp) + move $a2, $sp # pass $sp RETURN_IF_ZERO .global art_check_cast_from_code @@ -459,10 +447,10 @@ art_unlock_object_from_code: */ ALIGN_FUNCTION_ENTRY art_check_cast_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case exception allocation triggers GC - move a2, rSELF @ pass Thread::Current - jal artCheckCastFromCode @ (Class* a, Class* b, Thread*, SP) - move a3, sp @ pass SP + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case exception allocation triggers GC + move $a2, rSELF # pass Thread::Current + jal artCheckCastFromCode # (Class* a, Class* b, Thread*, $sp) + move $a3, $sp # pass $sp RETURN_IF_ZERO .global art_can_put_array_element_from_code @@ -473,10 +461,10 @@ art_check_cast_from_code: */ ALIGN_FUNCTION_ENTRY art_can_put_array_element_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case exception allocation triggers GC - move a2, rSELF @ pass Thread::Current - jal artCanPutArrayElementFromCode @ (Object* element, Class* array_class, Thread*, SP) - move a3, sp @ pass SP + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case exception allocation triggers GC + move $a2, rSELF # pass Thread::Current + jal artCanPutArrayElementFromCode # (Object* element, Class* array_class, Thread*, $sp) + move $a3, $sp # pass $sp RETURN_IF_ZERO .global art_initialize_static_storage_from_code @@ -488,11 +476,11 @@ art_can_put_array_element_from_code: */ ALIGN_FUNCTION_ENTRY art_initialize_static_storage_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - move a2, rSELF @ pass Thread::Current - @ artInitializeStaticStorageFromCode(uint32_t type_idx, Method* referrer, Thread*, SP) + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + move $a2, rSELF # pass Thread::Current + # artInitializeStaticStorageFromCode(uint32_t type_idx, Method* referrer, Thread*, $sp) jal artInitializeStaticStorageFromCode - move a3, sp @ pass SP + move $a3, $sp # pass $sp RETURN_IF_NONZERO .global art_initialize_type_from_code @@ -502,11 +490,11 @@ art_initialize_static_storage_from_code: */ ALIGN_FUNCTION_ENTRY art_initialize_type_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - move a2, rSELF @ pass Thread::Current - @ artInitializeTypeFromCode(uint32_t type_idx, Method* referrer, Thread*, SP) + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + move $a2, rSELF # pass Thread::Current + # artInitializeTypeFromCode(uint32_t type_idx, Method* referrer, Thread*, $sp) jal artInitializeTypeFromCode - move a3, sp @ pass SP + move $a3, $sp # pass $sp RETURN_IF_NONZERO .global art_initialize_type_and_verify_access_from_code @@ -517,11 +505,11 @@ art_initialize_type_from_code: */ ALIGN_FUNCTION_ENTRY art_initialize_type_and_verify_access_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - move a2, rSELF @ pass Thread::Current - @ artInitializeTypeFromCode(uint32_t type_idx, Method* referrer, Thread*, SP) + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + move $a2, rSELF # pass Thread::Current + # artInitializeTypeFromCode(uint32_t type_idx, Method* referrer, Thread*, $sp) jal artInitializeTypeAndVerifyAccessFromCode - move a3, sp @ pass SP + move $a3, $sp # pass $sp RETURN_IF_NONZERO .global art_get32_static_from_code @@ -531,11 +519,11 @@ art_initialize_type_and_verify_access_from_code: */ ALIGN_FUNCTION_ENTRY art_get32_static_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - lw a1, 48(sp) @ pass referrer's Method* - move a2, rSELF @ pass Thread::Current - jal artGet32StaticFromCode @ (uint32_t field_idx, const Method* referrer, Thread*, SP) - move a3, sp @ pass SP + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + lw $a1, 48($sp) # pass referrer's Method* + move $a2, rSELF # pass Thread::Current + jal artGet32StaticFromCode # (uint32_t field_idx, const Method* referrer, Thread*, $sp) + move $a3, $sp # pass $sp RETURN_IF_NO_EXCEPTION .global art_get64_static_from_code @@ -545,11 +533,11 @@ art_get32_static_from_code: */ ALIGN_FUNCTION_ENTRY art_get64_static_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - lw a1, 48(sp) @ pass referrer's Method* - move a2, rSELF @ pass Thread::Current - jal artGet64StaticFromCode @ (uint32_t field_idx, const Method* referrer, Thread*, SP) - move a3, sp @ pass SP + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + lw $a1, 48($sp) # pass referrer's Method* + move $a2, rSELF # pass Thread::Current + jal artGet64StaticFromCode # (uint32_t field_idx, const Method* referrer, Thread*, $sp) + move $a3, $sp # pass $sp RETURN_IF_NO_EXCEPTION .global art_get_obj_static_from_code @@ -559,11 +547,11 @@ art_get64_static_from_code: */ ALIGN_FUNCTION_ENTRY art_get_obj_static_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - lw a1, 48(sp) @ pass referrer's Method* - move a2, rSELF @ pass Thread::Current - jal artGetObjStaticFromCode @ (uint32_t field_idx, const Method* referrer, Thread*, SP) - move a3, sp @ pass SP + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + lw $a1, 48($sp) # pass referrer's Method* + move $a2, rSELF # pass Thread::Current + jal artGetObjStaticFromCode # (uint32_t field_idx, const Method* referrer, Thread*, $sp) + move $a3, $sp # pass $sp RETURN_IF_NO_EXCEPTION .global art_get32_instance_from_code @@ -573,11 +561,11 @@ art_get_obj_static_from_code: */ ALIGN_FUNCTION_ENTRY art_get32_instance_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - lw a2, 48(sp) @ pass referrer's Method* - move a3, rSELF @ pass Thread::Current - jal artGet32InstanceFromCode @ (field_idx, Object*, referrer, Thread*, SP) - sw sp, 0(sp) @ pass SP + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + lw $a2, 48($sp) # pass referrer's Method* + move $a3, rSELF # pass Thread::Current + jal artGet32InstanceFromCode # (field_idx, Object*, referrer, Thread*, $sp) + sw $sp, 0($sp) # pass $sp RETURN_IF_NO_EXCEPTION .global art_get64_instance_from_code @@ -587,11 +575,11 @@ art_get32_instance_from_code: */ ALIGN_FUNCTION_ENTRY art_get64_instance_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - lw a2, 48(sp) @ pass referrer's Method* - move a3, rSELF @ pass Thread::Current - jal artGet64InstanceFromCode @ (field_idx, Object*, referrer, Thread*, SP) - sw sp, 0(sp) @ pass SP + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + lw $a2, 48($sp) # pass referrer's Method* + move $a3, rSELF # pass Thread::Current + jal artGet64InstanceFromCode # (field_idx, Object*, referrer, Thread*, $sp) + sw $sp, 0($sp) # pass $sp RETURN_IF_NO_EXCEPTION .global art_get_obj_instance_from_code @@ -601,11 +589,11 @@ art_get64_instance_from_code: */ ALIGN_FUNCTION_ENTRY art_get_obj_instance_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - lw a2, 48(sp) @ pass referrer's Method* - move a3, rSELF @ pass Thread::Current - jal artGetObjInstanceFromCode @ (field_idx, Object*, referrer, Thread*, SP) - sw sp, 0(sp) @ pass SP + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + lw $a2, 48($sp) # pass referrer's Method* + move $a3, rSELF # pass Thread::Current + jal artGetObjInstanceFromCode # (field_idx, Object*, referrer, Thread*, $sp) + sw $sp, 0($sp) # pass $sp RETURN_IF_NO_EXCEPTION .global art_set32_static_from_code @@ -615,11 +603,11 @@ art_get_obj_instance_from_code: */ ALIGN_FUNCTION_ENTRY art_set32_static_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - lw a2, 48(sp) @ pass referrer's Method* - move a3, rSELF @ pass Thread::Current - jal artSet32StaticFromCode @ (field_idx, new_val, referrer, Thread*, SP) - sw sp, 0(sp) @ pass SP + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + lw $a2, 48($sp) # pass referrer's Method* + move $a3, rSELF # pass Thread::Current + jal artSet32StaticFromCode # (field_idx, new_val, referrer, Thread*, $sp) + sw $sp, 0($sp) # pass $sp RETURN_IF_ZERO .global art_set64_static_from_code @@ -629,14 +617,14 @@ art_set32_static_from_code: */ ALIGN_FUNCTION_ENTRY art_set64_static_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - lw a1, 48(sp) @ pass referrer's Method* - move t0, sp @ save SP - addui sp, sp, -16 - sw rSELF, 0(sp) @ pass Thread::Current and sp - jal artSet64StaticFromCode @ (field_idx, referrer, new_val, Thread*, SP) - sw t0, 4(sp) - addui sp, #16 @ release out args + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + lw $a1, 48($sp) # pass referrer's Method* + move $t0, $sp # save $sp + addiu $sp, $sp, -16 + sw rSELF, 0($sp) # pass Thread::Current and $sp + jal artSet64StaticFromCode # (field_idx, referrer, new_val, Thread*, $sp) + sw $t0, 4($sp) + addiu $sp, #16 # release out args RETURN_IF_ZERO .global art_set_obj_static_from_code @@ -646,11 +634,11 @@ art_set64_static_from_code: */ ALIGN_FUNCTION_ENTRY art_set_obj_static_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - lw a2, 48(sp) @ pass referrer's Method* - move a3, rSELF @ pass Thread::Current - jal artSetObjStaticFromCode @ (field_idx, new_val, referrer, Thread*, SP) - sw sp, 0(sp) @ pass SP + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + lw $a2, 48($sp) # pass referrer's Method* + move $a3, rSELF # pass Thread::Current + jal artSetObjStaticFromCode # (field_idx, new_val, referrer, Thread*, $sp) + sw $sp, 0($sp) # pass $sp RETURN_IF_ZERO .global art_set32_instance_from_code @@ -660,14 +648,14 @@ art_set_obj_static_from_code: */ ALIGN_FUNCTION_ENTRY art_set32_instance_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - lw a4, 48(sp) @ pass referrer's Method* - move t0, sp @ save SP - addui sp, sp, -16 - sw rSELF, 0(sp) @ pass Thread::Current and sp - jal artSet32InstanceFromCode @ (field_idx, Object*, new_val, referrer, Thread*, SP) - sw t0, 4(sp) - addiu sp, sp, 16 @ release out args + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + lw $a3, 48($sp) # pass referrer's Method* + move $t0, $sp # save $sp + addiu $sp, $sp, -16 + sw rSELF, 0($sp) # pass Thread::Current and $sp + jal artSet32InstanceFromCode # (field_idx, Object*, new_val, referrer, Thread*, $sp) + sw $t0, 4($sp) + addiu $sp, $sp, 16 # release out args RETURN_IF_ZERO .global art_set64_instance_from_code @@ -677,13 +665,13 @@ art_set32_instance_from_code: */ ALIGN_FUNCTION_ENTRY art_set64_instance_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - move t0, sp @ save SP - addui sp, sp, -16 - sw rSELF, 0(sp) @ pass Thread::Current and sp - jal artSet64InstanceFromCode @ (field_idx, Object*, new_val, Thread*, SP) - sw t0, 4(sp) - addiu sp, sp, 16 @ release out args + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + move $t0, $sp # save $sp + addiu $sp, $sp, -16 + sw rSELF, 0($sp) # pass Thread::Current and $sp + jal artSet64InstanceFromCode # (field_idx, Object*, new_val, Thread*, $sp) + sw $t0, 4($sp) + addiu $sp, $sp, 16 # release out args RETURN_IF_ZERO .global art_set_obj_instance_from_code @@ -693,14 +681,14 @@ art_set64_instance_from_code: */ ALIGN_FUNCTION_ENTRY art_set_obj_instance_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - lw a3, 48(sp) @ pass referrer's Method* - move t0, sp @ save SP - addui sp, sp, -16 - sw rSELF, 0(sp) @ pass Thread::Current and sp - jal artSetObjInstanceFromCode @ (field_idx, Object*, new_val, referrer, Thread*, SP) - sw t0, 4(sp) - addiu sp, sp, 16 @ release out args + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + lw $a3, 48($sp) # pass referrer's Method* + move $t0, $sp # save $sp + addiu $sp, $sp, -16 + sw rSELF, 0($sp) # pass Thread::Current and $sp + jal artSetObjInstanceFromCode # (field_idx, Object*, new_val, referrer, Thread*, $sp) + sw $t0, 4($sp) + addiu $sp, $sp, 16 # release out args RETURN_IF_ZERO .global art_resolve_string_from_code @@ -713,11 +701,11 @@ art_set_obj_instance_from_code: */ ALIGN_FUNCTION_ENTRY art_resolve_string_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - move a2, rSELF @ pass Thread::Current - @ artResolveStringFromCode(Method* referrer, uint32_t string_idx, Thread*, SP) + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + move $a2, rSELF # pass Thread::Current + # artResolveStringFromCode(Method* referrer, uint32_t string_idx, Thread*, $sp) jal artResolveStringFromCode - move a3, sp @ pass SP + move $a3, $sp # pass $sp RETURN_IF_ZERO .global art_alloc_object_from_code @@ -727,10 +715,10 @@ art_resolve_string_from_code: */ ALIGN_FUNCTION_ENTRY art_alloc_object_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - move a2, rSELF @ pass Thread::Current - jal artAllocObjectFromCode @ (uint32_t type_idx, Method* method, Thread*, SP) - move a3, sp @ pass SP + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + move $a2, rSELF # pass Thread::Current + jal artAllocObjectFromCode # (uint32_t type_idx, Method* method, Thread*, $sp) + move $a3, $sp # pass $sp RETURN_IF_NONZERO .global art_alloc_object_from_code_with_access_check @@ -741,10 +729,10 @@ art_alloc_object_from_code: */ ALIGN_FUNCTION_ENTRY art_alloc_object_from_code_with_access_check: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - move a2, rSELF @ pass Thread::Current - jal artAllocObjectFromCodeWithAccessCheck @ (uint32_t type_idx, Method* method, Thread*, SP) - move a3, sp @ pass SP + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + move $a2, rSELF # pass Thread::Current + jal artAllocObjectFromCodeWithAccessCheck # (uint32_t type_idx, Method* method, Thread*, $sp) + move $a3, $sp # pass $sp RETURN_IF_NONZERO .global art_alloc_array_from_code @@ -754,11 +742,11 @@ art_alloc_object_from_code_with_access_check: */ ALIGN_FUNCTION_ENTRY art_alloc_array_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - move a3, r9 @ pass Thread::Current - @ artAllocArrayFromCode(uint32_t type_idx, Method* method, int32_t component_count, Thread*, SP) + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + move $a3, rSELF # pass Thread::Current + # artAllocArrayFromCode(uint32_t type_idx, Method* method, int32_t component_count, Thread*, $sp) jal artAllocArrayFromCode - sw sp, 0(sp) @ pass SP + sw $sp, 0($sp) # pass $sp RETURN_IF_NONZERO .global art_alloc_array_from_code_with_access_check @@ -769,11 +757,11 @@ art_alloc_array_from_code: */ ALIGN_FUNCTION_ENTRY art_alloc_array_from_code_with_access_check: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - move a3, rSELF @ pass Thread::Current - @ artAllocArrayFromCodeWithAccessCheck(type_idx, method, component_count, Thread*, SP) + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + move $a3, rSELF # pass Thread::Current + # artAllocArrayFromCodeWithAccessCheck(type_idx, method, component_count, Thread*, $sp) jal artAllocArrayFromCodeWithAccessCheck - sw sp, 0(sp) @ pass SP + sw $sp, 0($sp) # pass $sp RETURN_IF_NONZERO .global art_check_and_alloc_array_from_code @@ -783,11 +771,11 @@ art_alloc_array_from_code_with_access_check: */ ALIGN_FUNCTION_ENTRY art_check_and_alloc_array_from_code: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - move a3, rSELF @ pass Thread::Current - @ artCheckAndAllocArrayFromCode(uint32_t type_idx, Method* method, int32_t count, Thread* , SP) + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + move $a3, rSELF # pass Thread::Current + # artCheckAndAllocArrayFromCode(uint32_t type_idx, Method* method, int32_t count, Thread* , $sp) jal artCheckAndAllocArrayFromCode - sw sp, 0(sp) @ pass SP + sw $sp, 0($sp) # pass $sp RETURN_IF_NONZERO .global art_check_and_alloc_array_from_code_with_access_check @@ -797,11 +785,11 @@ art_check_and_alloc_array_from_code: */ ALIGN_FUNCTION_ENTRY art_check_and_alloc_array_from_code_with_access_check: - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves in case of GC - move a3, rSELF @ pass Thread::Current - @ artCheckAndAllocArrayFromCodeWithAccessCheck(type_idx, method, count, Thread* , SP) + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves in case of GC + move $a3, rSELF # pass Thread::Current + # artCheckAndAllocArrayFromCodeWithAccessCheck(type_idx, method, count, Thread* , $sp) jal artCheckAndAllocArrayFromCodeWithAccessCheck - sw sp, 0(sp) @ pass SP + sw $sp, 0($sp) # pass $sp RETURN_IF_NONZERO .global art_test_suspend @@ -811,16 +799,16 @@ art_check_and_alloc_array_from_code_with_access_check: */ ALIGN_FUNCTION_ENTRY art_test_suspend: - lw a0, THREAD_SUSPEND_COUNT_OFFSET(rSELF) - bnez a0, 1f - move rSUSPEND, SUSPEND_CHECK_INTERVAL @ reset rSUSPEND to SUSPEND_CHECK_INTERVAL - jr ra + lw $a0, THREAD_SUSPEND_COUNT_OFFSET(rSELF) + bnez $a0, 1f + addi rSUSPEND, $zero, SUSPEND_CHECK_INTERVAL # reset rSUSPEND to SUSPEND_CHECK_INTERVAL + jr $ra nop 1: - move a0, rSELF - SETUP_REF_ONLY_CALLEE_SAVE_FRAME @ save callee saves for stack crawl - jal artTestSuspendFromCode @ (Thread*, SP) - move a1, sp + move $a0, rSELF + SETUP_REF_ONLY_CALLEE_SAVE_FRAME # save callee saves for stack crawl + jal artTestSuspendFromCode # (Thread*, $sp) + move $a1, $sp RESTORE_REF_ONLY_CALLEE_SAVE_FRAME_AND_RETURN .global art_proxy_invoke_handler @@ -832,18 +820,18 @@ art_test_suspend: ALIGN_FUNCTION_ENTRY art_proxy_invoke_handler: SETUP_REF_AND_ARGS_CALLEE_SAVE_FRAME - sw a0, 0(sp) @ place proxy method at bottom of frame - move a2, rSELF @ pass Thread::Current - jalr artProxyInvokeHandler @ (Method* proxy method, receiver, Thread*, args...) - addui a3, sp, 12 @ pointer to r2/r3/LR/caller's Method**/out-args as second arg - lw t0, THREAD_EXCEPTION_OFFSET(rSELF) @ load Thread::Current()->exception_ -@FIXME - offsets here are probably wrong - lw ra, 44(sp) @ restore ra - lw v0, 12(sp) - lw v1, 14(sp) - bnez r0, 1f - addui sp, sp, 48 @ pop frame - jr ra + sw $a0, 0($sp) # place proxy method at bottom of frame + move $a2, rSELF # pass Thread::Current + jal artProxyInvokeHandler # (Method* proxy method, receiver, Thread*, args...) + addiu $a3, $sp, 12 # pointer to r2/r3/LR/caller's Method**/out-args as second arg + lw $t0, THREAD_EXCEPTION_OFFSET(rSELF) # load Thread::Current()->exception_ +#FIXME - offsets here are probably wrong + lw $ra, 44($sp) # restore $ra + lw $v0, 12($sp) + lw $v1, 14($sp) + bnez $t0, 1f + addiu $sp, $sp, 48 # pop frame + jr $ra nop 1: DELIVER_PENDING_EXCEPTION @@ -855,21 +843,21 @@ art_proxy_invoke_handler: */ ALIGN_FUNCTION_ENTRY art_trace_entry_from_code: - addui sp, sp, -16 - sw a0, 0(sp) - sw a1, 4(sp) - sw a2, 8(sp) - sw a3, 12(sp) - move a2, ra @ pass ra - jalr artTraceMethodEntryFromCode @ (Method*, Thread*, LR) - move a1, rSELF @ pass Thread::Current - move t0, v0 @ t0 holds reference to code - lw a0, 0(sp) - lw a1, 4(sp) - lw a2, 8(sp) - lw a3, 12(sp) - jalr t0 @ call method - addui sp, sp, 16 + addiu $sp, $sp, -16 + sw $a0, 0($sp) + sw $a1, 4($sp) + sw $a2, 8($sp) + sw $a3, 12($sp) + move $a2, $ra # pass $ra + jal artTraceMethodEntryFromCode # (Method*, Thread*, LR) + move $a1, rSELF # pass Thread::Current + move $t0, $v0 # $t0 holds reference to code + lw $a0, 0($sp) + lw $a1, 4($sp) + lw $a2, 8($sp) + lw $a3, 12($sp) + jalr $t0 # call method + addiu $sp, $sp, 16 /* intentional fallthrough */ .global art_trace_exit_from_code @@ -879,15 +867,15 @@ art_trace_entry_from_code: */ ALIGN_FUNCTION_ENTRY art_trace_exit_from_code: - addui sp, sp, -16 - sw v0, 0(sp) - jalr artTraceMethodExitFromCode @ () - sw v1, 4(sp) - move ra, v0 @ restore link register - lw v0, 0(sp) - lw v1, 4(sp) - jr ra @ return - addui sp, sp, 16 + addiu $sp, $sp, -16 + sw $v0, 0($sp) + jal artTraceMethodExitFromCode # () + sw $v1, 4($sp) + move $ra, $v0 # restore link register + lw $v0, 0($sp) + lw $v1, 4($sp) + jr $ra # return + addiu $sp, $sp, 16 .global art_shl_long /* @@ -896,23 +884,23 @@ art_trace_exit_from_code: * distance) is 32-bit. Also, Dalvik requires us to ignore all but the low * 6 bits. * On entry: - * a0: low word - * a1: high word - * a2: shift count + * $a0: low word + * $a1: high word + * $a2: shift count */ ALIGN_FUNCTION_ENTRY art_shl_long: /* shl-long vAA, vBB, vCC */ - sll v0, a0, a2 @ rlo<- alo << (shift&31) - not v1, a2 @ rhi<- 31-shift (shift is 5b) - srl a0, 1 - srl a0, v1 @ alo<- alo >> (32-(shift&31)) - sll v1, a1, a2 @ rhi<- ahi << (shift&31) - or v1, a0 @ rhi<- rhi | alo - andi a2, 0x20 @ shift< shift & 0x20 - movn v1, v0, a2 @ rhi<- rlo (if shift&0x20) - jr ra - movn v0, zero, a2 @ rlo<- 0 (if shift&0x20) + sll $v0, $a0, $a2 # rlo<- alo << (shift&31) + not $v1, $a2 # rhi<- 31-shift (shift is 5b) + srl $a0, 1 + srl $a0, $v1 # alo<- alo >> (32-(shift&31)) + sll $v1, $a1, $a2 # rhi<- ahi << (shift&31) + or $v1, $a0 # rhi<- rhi | alo + andi $a2, 0x20 # shift< shift & 0x20 + movn $v1, $v0, $a2 # rhi<- rlo (if shift&0x20) + jr $ra + movn $v0, $zero, $a2 # rlo<- 0 (if shift&0x20) .global art_shr_long /* @@ -921,23 +909,23 @@ art_shl_long: * distance) is 32-bit. Also, Dalvik requires us to ignore all but the low * 6 bits. * On entry: - * a0: low word - * a1: high word - * a2: shift count + * $a0: low word + * $a1: high word + * $a2: shift count */ ALIGN_FUNCTION_ENTRY art_shr_long: - sra v1, a1, a2 @ rhi<- ahi >> (shift&31) - srl v0, a0, a2 @ rlo<- alo >> (shift&31) - sra a3, a1, 31 @ a3<- sign(ah) - not a0, a2 @ alo<- 31-shift (shift is 5b) - sll a1, 1 - sll a1, a0 @ ahi<- ahi << (32-(shift&31)) - or v0, a1 @ rlo<- rlo | ahi - andi a2, 0x20 @ shift & 0x20 - movn v0, v1, a2 @ rlo<- rhi (if shift&0x20) - jr ra - movn v1, a3, a2 @ rhi<- sign(ahi) (if shift&0x20) + sra $v1, $a1, $a2 # rhi<- ahi >> (shift&31) + srl $v0, $a0, $a2 # rlo<- alo >> (shift&31) + sra $a3, $a1, 31 # $a3<- sign(ah) + not $a0, $a2 # alo<- 31-shift (shift is 5b) + sll $a1, 1 + sll $a1, $a0 # ahi<- ahi << (32-(shift&31)) + or $v0, $a1 # rlo<- rlo | ahi + andi $a2, 0x20 # shift & 0x20 + movn $v0, $v1, $a2 # rlo<- rhi (if shift&0x20) + jr $ra + movn $v1, $a3, $a2 # rhi<- sign(ahi) (if shift&0x20) .global art_ushr_long /* @@ -953,14 +941,24 @@ art_shr_long: /* ushr-long vAA, vBB, vCC */ ALIGN_FUNCTION_ENTRY art_ushr_long: - sra v1, a1, a2 @ rhi<- ahi >> (shift&31) - srl v0, a0, a2 @ rlo<- alo >> (shift&31) - sra a3, a1, 31 @ a3<- sign(ah) - not a0, a2 @ alo<- 31-shift (shift is 5b) - sll a1, 1 - sll a1, a0 @ ahi<- ahi << (32-(shift&31)) - or v0, a1 @ rlo<- rlo | ahi - andi a2, 0x20 @ shift & 0x20 - movn v0, v1, a2 @ rlo<- rhi (if shift&0x20) - jr ra - movn v1, a3, a2 @ rhi<- sign(ahi) (if shift&0x20) + sra $v1, $a1, $a2 # rhi<- ahi >> (shift&31) + srl $v0, $a0, $a2 # rlo<- alo >> (shift&31) + sra $a3, $a1, 31 # $a3<- sign(ah) + not $a0, $a2 # alo<- 31-shift (shift is 5b) + sll $a1, 1 + sll $a1, $a0 # ahi<- ahi << (32-(shift&31)) + or $v0, $a1 # rlo<- rlo | ahi + andi $a2, 0x20 # shift & 0x20 + movn $v0, $v1, $a2 # rlo<- rhi (if shift&0x20) + jr $ra + movn $v1, $a3, $a2 # rhi<- sign(ahi) (if shift&0x20) + + .global art_indexof + ALIGN_FUNCTION_ENTRY +art_indexof: + jr $ra + + .global art_string_compareto + ALIGN_FUNCTION_ENTRY +art_string_compareto: + jr $ra diff --git a/src/oat/runtime/mips/stub_mips.cc b/src/oat/runtime/mips/stub_mips.cc new file mode 100644 index 0000000000..38a1586bd4 --- /dev/null +++ b/src/oat/runtime/mips/stub_mips.cc @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "jni_internal.h" +#include "oat/runtime/oat_support_entrypoints.h" +#include "oat/runtime/stub.h" +#include "oat/utils/mips/assembler_mips.h" +#include "object.h" +#include "stack_indirect_reference_table.h" + +#define __ assembler-> + +namespace art { +namespace mips { + +ByteArray* MipsCreateResolutionTrampoline(Runtime::TrampolineType type) { + UniquePtr<MipsAssembler> assembler(static_cast<MipsAssembler*>(Assembler::Create(kMips))); +#if !defined(ART_USE_LLVM_COMPILER) + // | Out args | + // | Method* | <- SP on entry + // | RA | return address into caller + // | ... | callee saves + // | A3 | possible argument + // | A2 | possible argument + // | A1 | possible argument + // | A0 | junk on call to UnresolvedDirectMethodTrampolineFromCode, holds result Method* + // | Method* | Callee save Method* set up by UnresolvedDirectMethodTrampolineFromCode + // Save callee saves and ready frame for exception delivery + __ AddConstant(SP, SP, -64); + __ StoreToOffset(kStoreWord, RA, SP, 60); + __ StoreToOffset(kStoreWord, T9, SP, 56); + __ StoreToOffset(kStoreWord, T8, SP, 52); + __ StoreToOffset(kStoreWord, T7, SP, 48); + __ StoreToOffset(kStoreWord, T6, SP, 44); + __ StoreToOffset(kStoreWord, T5, SP, 40); + __ StoreToOffset(kStoreWord, T4, SP, 36); + __ StoreToOffset(kStoreWord, T3, SP, 32); + __ StoreToOffset(kStoreWord, T2, SP, 28); + __ StoreToOffset(kStoreWord, T1, SP, 24); + __ StoreToOffset(kStoreWord, T0, SP, 20); + __ StoreToOffset(kStoreWord, A3, SP, 16); + __ StoreToOffset(kStoreWord, A2, SP, 12); + __ StoreToOffset(kStoreWord, A1, SP, 8); + + __ LoadFromOffset(kLoadWord, T9, S1, + ENTRYPOINT_OFFSET(pUnresolvedDirectMethodTrampolineFromCode)); + __ Move(A2, S1); // Pass Thread::Current() in A2 + __ LoadImmediate(A3, type); // Pass is_static + __ Move(A1, SP); // Pass SP for Method** callee_addr + __ Jalr(T9); // Call to unresolved direct method trampoline (method_idx, sp, Thread*, is_static) + + // Restore registers which may have been modified by GC + __ LoadFromOffset(kLoadWord, A1, SP, 8); + __ LoadFromOffset(kLoadWord, A2, SP, 12); + __ LoadFromOffset(kLoadWord, A3, SP, 16); + __ LoadFromOffset(kLoadWord, T0, SP, 20); + __ LoadFromOffset(kLoadWord, T1, SP, 24); + __ LoadFromOffset(kLoadWord, T2, SP, 28); + __ LoadFromOffset(kLoadWord, T3, SP, 32); + __ LoadFromOffset(kLoadWord, T4, SP, 36); + __ LoadFromOffset(kLoadWord, T5, SP, 40); + __ LoadFromOffset(kLoadWord, T6, SP, 44); + __ LoadFromOffset(kLoadWord, T7, SP, 48); + __ LoadFromOffset(kLoadWord, T8, SP, 52); + __ LoadFromOffset(kLoadWord, T9, SP, 56); + __ LoadFromOffset(kLoadWord, RA, SP, 60); + __ AddConstant(SP, SP, 64); + + __ Move(A0, V0); // Put returned Method* into A0 + __ Jr(V0); // Leaf call to method's code + + __ Break(); +#else // ART_USE_LLVM_COMPILER + // Build frame and save argument registers and RA. + __ AddConstant(SP, SP, -32); + __ StoreToOffset(kStoreWord, RA, SP, 28); + __ StoreToOffset(kStoreWord, A3, SP, 24); + __ StoreToOffset(kStoreWord, A2, SP, 20); + __ StoreToOffset(kStoreWord, A1, SP, 16); + __ StoreToOffset(kStoreWord, A0, SP, 12); + + __ LoadFromOffset(kLoadWord, T9, S1, + ENTRYPOINT_OFFSET(pUnresolvedDirectMethodTrampolineFromCode)); + __ mov(A2, S1); // Pass Thread::Current() in A2 + __ LoadImmediate(A3, type); // Pass is_static + __ mov(A1, SP); // Pass SP for Method** callee_addr + __ Jalr(T9); // Call to unresolved direct method trampoline (callee, callee_addr, Thread*, is_static) + + // Restore frame, argument registers, and RA. + __ LoadFromOffset(kLoadWord, A0, SP, 12); + __ LoadFromOffset(kLoadWord, A1, SP, 16); + __ LoadFromOffset(kLoadWord, A2, SP, 20); + __ LoadFromOffset(kLoadWord, A3, SP, 24); + __ LoadFromOffset(kLoadWord, RA, SP, 28); + __ AddConstant(SP, SP, 32); + + Label resolve_fail; + __ EmitBranch(V0, ZERO, &resolve_fail, true); + __ Jr(V0); // If V0 != 0 tail call method's code + __ Bind(&resolve_fail, false); + __ Jr(RA); // Return to caller to handle exception +#endif // ART_USE_LLVM_COMPILER + + assembler->EmitSlowPaths(); + + size_t cs = assembler->CodeSize(); + SirtRef<ByteArray> resolution_trampoline(ByteArray::Alloc(cs)); + CHECK(resolution_trampoline.get() != NULL); + MemoryRegion code(resolution_trampoline->GetData(), resolution_trampoline->GetLength()); + assembler->FinalizeInstructions(code); + + return resolution_trampoline.get(); +} + +typedef void (*ThrowAme)(Method*, Thread*); + +ByteArray* CreateAbstractMethodErrorStub() { + UniquePtr<MipsAssembler> assembler(static_cast<MipsAssembler*>(Assembler::Create(kMips))); +#if !defined(ART_USE_LLVM_COMPILER) + // Save callee saves and ready frame for exception delivery + __ AddConstant(SP, SP, -176); + __ StoreToOffset(kStoreWord, RA, SP, 172); + __ StoreToOffset(kStoreWord, T9, SP, 168); + __ StoreToOffset(kStoreWord, T8, SP, 164); + __ StoreToOffset(kStoreWord, T7, SP, 160); + __ StoreToOffset(kStoreWord, T6, SP, 156); + __ StoreToOffset(kStoreWord, T5, SP, 152); + __ StoreToOffset(kStoreWord, T4, SP, 148); + __ StoreToOffset(kStoreWord, T3, SP, 144); + __ StoreToOffset(kStoreWord, T2, SP, 140); + __ StoreToOffset(kStoreWord, T1, SP, 136); + __ StoreToOffset(kStoreWord, T0, SP, 132); + __ StoreDToOffset(D15, SP, 124); + __ StoreDToOffset(D14, SP, 116); + __ StoreDToOffset(D13, SP, 108); + __ StoreDToOffset(D12, SP, 100); + __ StoreDToOffset(D11, SP, 92); + __ StoreDToOffset(D10, SP, 84); + __ StoreDToOffset(D9, SP, 76); + __ StoreDToOffset(D8, SP, 68); + __ StoreDToOffset(D7, SP, 60); + __ StoreDToOffset(D6, SP, 52); + __ StoreDToOffset(D5, SP, 44); + __ StoreDToOffset(D4, SP, 36); + __ StoreDToOffset(D3, SP, 28); + __ StoreDToOffset(D2, SP, 20); + __ StoreDToOffset(D1, SP, 12); + __ StoreDToOffset(D0, SP, 4); + + // R0 is the Method* already + __ Move(A1, S1); // Pass Thread::Current() in A1 + __ Move(A2, SP); // Pass SP in A2 + // Call to throw AbstractMethodError + __ LoadFromOffset(kLoadWord, T9, S1, ENTRYPOINT_OFFSET(pThrowAbstractMethodErrorFromCode)); + __ Jr(T9); // Leaf call to routine that never returns + + __ Break(); +#else // ART_USE_LLVM_COMPILER + // R0 is the Method* already + __ Move(A1, S1); // Pass Thread::Current() in A1 + // Call to throw AbstractMethodError + __ LoadFromOffset(kLoadWord, T9, S1, ENTRYPOINT_OFFSET(pThrowAbstractMethodErrorFromCode)); + __ Jr(T9); // Leaf call to routine that never returns + + __ Break(); +#endif // ART_USE_LLVM_COMPILER + + assembler->EmitSlowPaths(); + + size_t cs = assembler->CodeSize(); + SirtRef<ByteArray> abstract_stub(ByteArray::Alloc(cs)); + CHECK(abstract_stub.get() != NULL); + MemoryRegion code(abstract_stub->GetData(), abstract_stub->GetLength()); + assembler->FinalizeInstructions(code); + + return abstract_stub.get(); +} + +ByteArray* CreateJniDlsymLookupStub() { + UniquePtr<MipsAssembler> assembler(static_cast<MipsAssembler*>(Assembler::Create(kMips))); + + // Build frame and save argument registers and RA. + __ AddConstant(SP, SP, -32); + __ StoreToOffset(kStoreWord, RA, SP, 28); + __ StoreToOffset(kStoreWord, A3, SP, 24); + __ StoreToOffset(kStoreWord, A2, SP, 20); + __ StoreToOffset(kStoreWord, A1, SP, 16); + __ StoreToOffset(kStoreWord, A0, SP, 12); + + __ Move(A0, S1); // Pass Thread::Current() in A0 + __ LoadFromOffset(kLoadWord, T9, S1, ENTRYPOINT_OFFSET(pFindNativeMethod)); + __ Jalr(T9); // Call FindNativeMethod + + // Restore frame, argument registers, and RA. + __ LoadFromOffset(kLoadWord, A0, SP, 12); + __ LoadFromOffset(kLoadWord, A1, SP, 16); + __ LoadFromOffset(kLoadWord, A2, SP, 20); + __ LoadFromOffset(kLoadWord, A3, SP, 24); + __ LoadFromOffset(kLoadWord, RA, SP, 28); + __ AddConstant(SP, SP, 32); + + Label no_native_code_found; + __ EmitBranch(V0, ZERO, &no_native_code_found, true); + __ Jr(V0); // If V0 != 0 tail call method's code + __ Bind(&no_native_code_found, false); + __ Jr(RA); // Return to caller to handle exception + + assembler->EmitSlowPaths(); + + size_t cs = assembler->CodeSize(); + SirtRef<ByteArray> jni_stub(ByteArray::Alloc(cs)); + CHECK(jni_stub.get() != NULL); + MemoryRegion code(jni_stub->GetData(), jni_stub->GetLength()); + assembler->FinalizeInstructions(code); + + return jni_stub.get(); +} + +} // namespace mips +} // namespace art diff --git a/src/oat/runtime/stub.h b/src/oat/runtime/stub.h index 5d8b37d69c..9e5e66fa6b 100644 --- a/src/oat/runtime/stub.h +++ b/src/oat/runtime/stub.h @@ -30,6 +30,15 @@ namespace arm { SHARED_LOCKS_REQUIRED(GlobalSynchronization::mutator_lock_); } +namespace mips { + ByteArray* CreateAbstractMethodErrorStub() + SHARED_LOCKS_REQUIRED(GlobalSynchronization::mutator_lock_); + ByteArray* MipsCreateResolutionTrampoline(Runtime::TrampolineType type) + SHARED_LOCKS_REQUIRED(GlobalSynchronization::mutator_lock_); + ByteArray* CreateJniDlsymLookupStub() + SHARED_LOCKS_REQUIRED(GlobalSynchronization::mutator_lock_); +} + namespace x86 { ByteArray* CreateAbstractMethodErrorStub() SHARED_LOCKS_REQUIRED(GlobalSynchronization::mutator_lock_); diff --git a/src/oat/runtime/support_proxy.cc b/src/oat/runtime/support_proxy.cc index 972779d178..c22448479d 100644 --- a/src/oat/runtime/support_proxy.cc +++ b/src/oat/runtime/support_proxy.cc @@ -28,6 +28,10 @@ #define SP_OFFSET_IN_BYTES 12 #define FRAME_SIZE_IN_BYTES 48u #define ARG2_OFFSET_IN_WORDS 11 // offset to 3rd arg; skip callee saves, LR, Method* and out arg spills for OUT0 to OUT2 +#elif defined(__mips__) +#define SP_OFFSET_IN_BYTES 8 +#define FRAME_SIZE_IN_BYTES 32u +#define ARG2_OFFSET_IN_WORDS 8 // offset to 3rd arg; skip callee saves, LR, Method* and out arg spills for OUT0 to OUT2 #elif defined(__i386__) #define SP_OFFSET_IN_BYTES 8 #define FRAME_SIZE_IN_BYTES 32u diff --git a/src/oat/utils/assembler.cc b/src/oat/utils/assembler.cc index 249a771d84..92ce0b8001 100644 --- a/src/oat/utils/assembler.cc +++ b/src/oat/utils/assembler.cc @@ -20,6 +20,7 @@ #include <vector> #include "arm/assembler_arm.h" +#include "mips/assembler_mips.h" #include "x86/assembler_x86.h" #include "globals.h" #include "memory_region.h" @@ -101,11 +102,17 @@ void AssemblerBuffer::ExtendCapacity() { Assembler* Assembler::Create(InstructionSet instruction_set) { - if (instruction_set == kX86) { - return new x86::X86Assembler(); - } else { - CHECK(instruction_set == kArm || instruction_set == kThumb2); - return new arm::ArmAssembler(); + switch (instruction_set) { + case kArm: + case kThumb2: + return new arm::ArmAssembler(); + case kMips: + return new mips::MipsAssembler(); + case kX86: + return new x86::X86Assembler(); + default: + LOG(FATAL) << "Unknown InstructionSet: " << instruction_set; + return NULL; } } diff --git a/src/oat/utils/assembler.h b/src/oat/utils/assembler.h index 68108e7508..a1e3914e10 100644 --- a/src/oat/utils/assembler.h +++ b/src/oat/utils/assembler.h @@ -20,6 +20,7 @@ #include <vector> #include "constants_arm.h" +#include "constants_mips.h" #include "constants_x86.h" #include "instruction_set.h" #include "logging.h" @@ -37,6 +38,9 @@ class AssemblerFixup; namespace arm { class ArmAssembler; } +namespace mips { + class MipsAssembler; +} namespace x86 { class X86Assembler; } @@ -86,6 +90,7 @@ class Label { } friend class arm::ArmAssembler; + friend class mips::MipsAssembler; friend class x86::X86Assembler; DISALLOW_COPY_AND_ASSIGN(Label); diff --git a/src/oat/utils/managed_register.h b/src/oat/utils/managed_register.h index c0fbd21474..a3d5795665 100644 --- a/src/oat/utils/managed_register.h +++ b/src/oat/utils/managed_register.h @@ -19,12 +19,15 @@ namespace art { -namespace x86 { -class X86ManagedRegister; -} namespace arm { class ArmManagedRegister; } +namespace mips { +class MipsManagedRegister; +} +namespace x86 { +class X86ManagedRegister; +} class ManagedRegister { public: @@ -38,8 +41,9 @@ class ManagedRegister { return *this; } - x86::X86ManagedRegister AsX86() const; arm::ArmManagedRegister AsArm() const; + mips::MipsManagedRegister AsMips() const; + x86::X86ManagedRegister AsX86() const; // It is valid to invoke Equals on and with a NoRegister. bool Equals(const ManagedRegister& other) const { diff --git a/src/oat/utils/mips/assembler_mips.cc b/src/oat/utils/mips/assembler_mips.cc new file mode 100644 index 0000000000..60a81760fd --- /dev/null +++ b/src/oat/utils/mips/assembler_mips.cc @@ -0,0 +1,1042 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "assembler_mips.h" + +#include "casts.h" +#include "memory_region.h" +#include "oat/runtime/oat_support_entrypoints.h" +#include "thread.h" + +namespace art { +namespace mips { +#if 0 +class DirectCallRelocation : public AssemblerFixup { + public: + void Process(const MemoryRegion& region, int position) { + // Direct calls are relative to the following instruction on mips. + int32_t pointer = region.Load<int32_t>(position); + int32_t start = reinterpret_cast<int32_t>(region.start()); + int32_t delta = start + position + sizeof(int32_t); + region.Store<int32_t>(position, pointer - delta); + } +}; +#endif + +static const char* kRegisterNames[] = { + "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra", +}; +std::ostream& operator<<(std::ostream& os, const Register& rhs) { + if (rhs >= ZERO && rhs <= RA) { + os << kRegisterNames[rhs]; + } else { + os << "Register[" << static_cast<int>(rhs) << "]"; + } + return os; +} + +std::ostream& operator<<(std::ostream& os, const FRegister& rhs) { + if (rhs >= F0 && rhs < kNumberOfFRegisters) { + os << "f" << static_cast<int>(rhs); + } else { + os << "FRegister[" << static_cast<int>(rhs) << "]"; + } + return os; +} + +std::ostream& operator<<(std::ostream& os, const DRegister& rhs) { + if (rhs >= D0 && rhs < kNumberOfDRegisters) { + os << "d" << static_cast<int>(rhs); + } else { + os << "DRegister[" << static_cast<int>(rhs) << "]"; + } + return os; +} + +void MipsAssembler::Emit(int32_t value) { + AssemblerBuffer::EnsureCapacity ensured(&buffer_); + buffer_.Emit<int32_t>(value); +} + +void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) { + CHECK_NE(rs, kNoRegister); + CHECK_NE(rt, kNoRegister); + CHECK_NE(rd, kNoRegister); + int32_t encoding = opcode << kOpcodeShift | + static_cast<int32_t>(rs) << kRsShift | + static_cast<int32_t>(rt) << kRtShift | + static_cast<int32_t>(rd) << kRdShift | + shamt << kShamtShift | + funct; + Emit(encoding); +} + +void MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { + CHECK_NE(rs, kNoRegister); + CHECK_NE(rt, kNoRegister); + int32_t encoding = opcode << kOpcodeShift | + static_cast<int32_t>(rs) << kRsShift | + static_cast<int32_t>(rt) << kRtShift | + imm; + Emit(encoding); +} + +void MipsAssembler::EmitJ(int opcode, int address) { + int32_t encoding = opcode << kOpcodeShift | + address; + Emit(encoding); +} + +void MipsAssembler::EmitFR(int opcode, int fmt, FRegister ft, FRegister fs, FRegister fd, int funct) { + CHECK_NE(ft, kNoFRegister); + CHECK_NE(fs, kNoFRegister); + CHECK_NE(fd, kNoFRegister); + int32_t encoding = opcode << kOpcodeShift | + fmt << kFmtShift | + static_cast<int32_t>(ft) << kFtShift | + static_cast<int32_t>(fs) << kFsShift | + static_cast<int32_t>(fd) << kFdShift | + funct; + Emit(encoding); +} + +void MipsAssembler::EmitFI(int opcode, int fmt, FRegister rt, uint16_t imm) { + CHECK_NE(rt, kNoFRegister); + int32_t encoding = opcode << kOpcodeShift | + fmt << kFmtShift | + static_cast<int32_t>(rt) << kRtShift | + imm; + Emit(encoding); +} + +void MipsAssembler::EmitBranch(Register rt, Register rs, Label* label, bool equal) { + int offset; + if (label->IsBound()) { + offset = label->Position() - buffer_.Size(); + } else { + // Use the offset field of the branch instruction for linking the sites. + offset = label->position_; + label->LinkTo(buffer_.Size()); + } + if (equal) { + Beq(rt, rs, (offset >> 2) & kBranchOffsetMask); + } else { + Bne(rt, rs, (offset >> 2) & kBranchOffsetMask); + } +} + +void MipsAssembler::EmitJump(Label* label, bool link) { + int offset; + if (label->IsBound()) { + offset = label->Position() - buffer_.Size(); + } else { + // Use the offset field of the jump instruction for linking the sites. + offset = label->position_; + label->LinkTo(buffer_.Size()); + } + if (link) { + Jal((offset >> 2) & kJumpOffsetMask); + } else { + J((offset >> 2) & kJumpOffsetMask); + } +} + +int32_t MipsAssembler::EncodeBranchOffset(int offset, int32_t inst, bool is_jump) { + CHECK_ALIGNED(offset, 4); + CHECK(IsInt(CountOneBits(kBranchOffsetMask), offset)) << offset; + + // Properly preserve only the bits supported in the instruction. + offset >>= 2; + if (is_jump) { + offset &= kJumpOffsetMask; + return (inst & ~kJumpOffsetMask) | offset; + } else { + offset &= kBranchOffsetMask; + return (inst & ~kBranchOffsetMask) | offset; + } +} + +int MipsAssembler::DecodeBranchOffset(int32_t inst, bool is_jump) { + // Sign-extend, then left-shift by 2. + if (is_jump) { + return (((inst & kJumpOffsetMask) << 6) >> 4); + } else { + return (((inst & kBranchOffsetMask) << 16) >> 14); + } +} + +void MipsAssembler::Bind(Label* label, bool is_jump) { + CHECK(!label->IsBound()); + int bound_pc = buffer_.Size(); + while (label->IsLinked()) { + int32_t position = label->Position(); + int32_t next = buffer_.Load<int32_t>(position); + int32_t offset = is_jump ? bound_pc - position : bound_pc - position - 4; + int32_t encoded = MipsAssembler::EncodeBranchOffset(offset, next, is_jump); + buffer_.Store<int32_t>(position, encoded); + label->position_ = MipsAssembler::DecodeBranchOffset(next, is_jump); + } + label->BindTo(bound_pc); +} + +void MipsAssembler::Add(Register rd, Register rs, Register rt) { + EmitR(0, rs, rt, rd, 0, 0x20); +} + +void MipsAssembler::Addu(Register rd, Register rs, Register rt) { + EmitR(0, rs, rt, rd, 0, 0x21); +} + +void MipsAssembler::Addi(Register rt, Register rs, uint16_t imm16) { + EmitI(0x8, rs, rt, imm16); +} + +void MipsAssembler::Addiu(Register rt, Register rs, uint16_t imm16) { + EmitI(0x9, rs, rt, imm16); +} + +void MipsAssembler::Sub(Register rd, Register rs, Register rt) { + EmitR(0, rs, rt, rd, 0, 0x22); +} + +void MipsAssembler::Subu(Register rd, Register rs, Register rt) { + EmitR(0, rs, rt, rd, 0, 0x23); +} + +void MipsAssembler::Mult(Register rs, Register rt) { + EmitR(0, rs, rt, static_cast<Register>(0), 0, 0x18); +} + +void MipsAssembler::Multu(Register rs, Register rt) { + EmitR(0, rs, rt, static_cast<Register>(0), 0, 0x19); +} + +void MipsAssembler::Div(Register rs, Register rt) { + EmitR(0, rs, rt, static_cast<Register>(0), 0, 0x1a); +} + +void MipsAssembler::Divu(Register rs, Register rt) { + EmitR(0, rs, rt, static_cast<Register>(0), 0, 0x1b); +} + +void MipsAssembler::And(Register rd, Register rs, Register rt) { + EmitR(0, rs, rt, rd, 0, 0x24); +} + +void MipsAssembler::Andi(Register rt, Register rs, uint16_t imm16) { + EmitI(0xc, rs, rt, imm16); +} + +void MipsAssembler::Or(Register rd, Register rs, Register rt) { + EmitR(0, rs, rt, rd, 0, 0x25); +} + +void MipsAssembler::Ori(Register rt, Register rs, uint16_t imm16) { + EmitI(0xd, rs, rt, imm16); +} + +void MipsAssembler::Xor(Register rd, Register rs, Register rt) { + EmitR(0, rs, rt, rd, 0, 0x26); +} + +void MipsAssembler::Xori(Register rt, Register rs, uint16_t imm16) { + EmitI(0xe, rs, rt, imm16); +} + +void MipsAssembler::Nor(Register rd, Register rs, Register rt) { + EmitR(0, rs, rt, rd, 0, 0x27); +} + +void MipsAssembler::Sll(Register rd, Register rs, int shamt) { + EmitR(0, rs, static_cast<Register>(0), rd, shamt, 0x00); +} + +void MipsAssembler::Srl(Register rd, Register rs, int shamt) { + EmitR(0, rs, static_cast<Register>(0), rd, shamt, 0x02); +} + +void MipsAssembler::Sra(Register rd, Register rs, int shamt) { + EmitR(0, rs, static_cast<Register>(0), rd, shamt, 0x03); +} + +void MipsAssembler::Sllv(Register rd, Register rs, Register rt) { + EmitR(0, rs, rt, rd, 0, 0x04); +} + +void MipsAssembler::Srlv(Register rd, Register rs, Register rt) { + EmitR(0, rs, rt, rd, 0, 0x06); +} + +void MipsAssembler::Srav(Register rd, Register rs, Register rt) { + EmitR(0, rs, rt, rd, 0, 0x07); +} + +void MipsAssembler::Lb(Register rt, Register rs, uint16_t imm16) { + EmitI(0x20, rs, rt, imm16); +} + +void MipsAssembler::Lh(Register rt, Register rs, uint16_t imm16) { + EmitI(0x21, rs, rt, imm16); +} + +void MipsAssembler::Lw(Register rt, Register rs, uint16_t imm16) { + EmitI(0x23, rs, rt, imm16); +} + +void MipsAssembler::Lbu(Register rt, Register rs, uint16_t imm16) { + EmitI(0x24, rs, rt, imm16); +} + +void MipsAssembler::Lhu(Register rt, Register rs, uint16_t imm16) { + EmitI(0x25, rs, rt, imm16); +} + +void MipsAssembler::Lui(Register rt, uint16_t imm16) { + EmitI(0xf, static_cast<Register>(0), rt, imm16); +} + +void MipsAssembler::Mfhi(Register rd) { + EmitR(0, static_cast<Register>(0), static_cast<Register>(0), rd, 0, 0x10); +} + +void MipsAssembler::Mflo(Register rd) { + EmitR(0, static_cast<Register>(0), static_cast<Register>(0), rd, 0, 0x12); +} + +void MipsAssembler::Sb(Register rt, Register rs, uint16_t imm16) { + EmitI(0x28, rs, rt, imm16); +} + +void MipsAssembler::Sh(Register rt, Register rs, uint16_t imm16) { + EmitI(0x29, rs, rt, imm16); +} + +void MipsAssembler::Sw(Register rt, Register rs, uint16_t imm16) { + EmitI(0x2b, rs, rt, imm16); +} + +void MipsAssembler::Slt(Register rd, Register rs, Register rt) { + EmitR(0, rs, rt, rd, 0, 0x2a); +} + +void MipsAssembler::Sltu(Register rd, Register rs, Register rt) { + EmitR(0, rs, rt, rd, 0, 0x2b); +} + +void MipsAssembler::Slti(Register rt, Register rs, uint16_t imm16) { + EmitI(0xa, rs, rt, imm16); +} + +void MipsAssembler::Sltiu(Register rt, Register rs, uint16_t imm16) { + EmitI(0xb, rs, rt, imm16); +} + +void MipsAssembler::Beq(Register rt, Register rs, uint16_t imm16) { + EmitI(0x4, rs, rt, imm16); +} + +void MipsAssembler::Bne(Register rt, Register rs, uint16_t imm16) { + EmitI(0x5, rs, rt, imm16); +} + +void MipsAssembler::J(uint32_t address) { + EmitJ(0x2, address); +} + +void MipsAssembler::Jal(uint32_t address) { + EmitJ(0x2, address); +} + +void MipsAssembler::Jr(Register rs) { + EmitR(0, rs, static_cast<Register>(0), static_cast<Register>(0), 0, 0x08); +} + +void MipsAssembler::Jalr(Register rs) { + EmitR(0, rs, static_cast<Register>(0), static_cast<Register>(0), 0, 0x09); +} + +void MipsAssembler::AddS(FRegister fd, FRegister fs, FRegister ft) { + EmitFR(0x11, 0x10, ft, fs, fd, 0x0); +} + +void MipsAssembler::SubS(FRegister fd, FRegister fs, FRegister ft) { + EmitFR(0x11, 0x10, ft, fs, fd, 0x1); +} + +void MipsAssembler::MulS(FRegister fd, FRegister fs, FRegister ft) { + EmitFR(0x11, 0x10, ft, fs, fd, 0x2); +} + +void MipsAssembler::DivS(FRegister fd, FRegister fs, FRegister ft) { + EmitFR(0x11, 0x10, ft, fs, fd, 0x3); +} + +void MipsAssembler::AddD(DRegister fd, DRegister fs, DRegister ft) { + EmitFR(0x11, 0x11, static_cast<FRegister>(ft), static_cast<FRegister>(fs), + static_cast<FRegister>(fd), 0x0); +} + +void MipsAssembler::SubD(DRegister fd, DRegister fs, DRegister ft) { + EmitFR(0x11, 0x11, static_cast<FRegister>(ft), static_cast<FRegister>(fs), + static_cast<FRegister>(fd), 0x1); +} + +void MipsAssembler::MulD(DRegister fd, DRegister fs, DRegister ft) { + EmitFR(0x11, 0x11, static_cast<FRegister>(ft), static_cast<FRegister>(fs), + static_cast<FRegister>(fd), 0x2); +} + +void MipsAssembler::DivD(DRegister fd, DRegister fs, DRegister ft) { + EmitFR(0x11, 0x11, static_cast<FRegister>(ft), static_cast<FRegister>(fs), + static_cast<FRegister>(fd), 0x3); +} + +void MipsAssembler::MovS(FRegister fd, FRegister fs) { + EmitFR(0x11, 0x10, static_cast<FRegister>(0), fs, fd, 0x6); +} + +void MipsAssembler::MovD(DRegister fd, DRegister fs) { + EmitFR(0x11, 0x11, static_cast<FRegister>(0), static_cast<FRegister>(fs), + static_cast<FRegister>(fd), 0x6); +} + +void MipsAssembler::Mfc1(Register rt, FRegister fs) { + EmitFR(0x11, 0x00, static_cast<FRegister>(rt), fs, static_cast<FRegister>(0), 0x0); +} + +void MipsAssembler::Mtc1(FRegister ft, Register rs) { + EmitFR(0x11, 0x04, ft, static_cast<FRegister>(rs), static_cast<FRegister>(0), 0x0); +} + +void MipsAssembler::Lwc1(FRegister ft, Register rs, uint16_t imm16) { + EmitI(0x31, rs, static_cast<Register>(ft), imm16); +} + +void MipsAssembler::Ldc1(DRegister ft, Register rs, uint16_t imm16) { + EmitI(0x35, rs, static_cast<Register>(ft), imm16); +} + +void MipsAssembler::Swc1(FRegister ft, Register rs, uint16_t imm16) { + EmitI(0x39, rs, static_cast<Register>(ft), imm16); +} + +void MipsAssembler::Sdc1(DRegister ft, Register rs, uint16_t imm16) { + EmitI(0x3d, rs, static_cast<Register>(ft), imm16); +} + +void MipsAssembler::Break() { + EmitR(0, static_cast<Register>(0), static_cast<Register>(0), + static_cast<Register>(0), 0, 0xD); +} + +void MipsAssembler::Move(Register rt, Register rs) { + EmitI(0x8, rs, rt, 0); +} + +void MipsAssembler::Clear(Register rt) { + EmitR(0, static_cast<Register>(0), static_cast<Register>(0), rt, 0, 0x20); +} + +void MipsAssembler::Not(Register rt, Register rs) { + EmitR(0, static_cast<Register>(0), rs, rt, 0, 0x27); +} + +void MipsAssembler::Mul(Register rd, Register rs, Register rt) { + Mult(rs, rt); + Mflo(rd); +} + +void MipsAssembler::Div(Register rd, Register rs, Register rt) { + Div(rs, rt); + Mflo(rd); +} + +void MipsAssembler::Rem(Register rd, Register rs, Register rt) { + Div(rs, rt); + Mfhi(rd); +} + +void MipsAssembler::AddConstant(Register rt, Register rs, int32_t value) { + Addi(rt, rs, value); +} + +void MipsAssembler::LoadImmediate(Register rt, int32_t value) { + Addi(rt, ZERO, value); +} + +void MipsAssembler::EmitLoad(ManagedRegister m_dst, Register src_register, int32_t src_offset, + size_t size) { + MipsManagedRegister dst = m_dst.AsMips(); + if (dst.IsNoRegister()) { + CHECK_EQ(0u, size) << dst; + } else if (dst.IsCoreRegister()) { + CHECK_EQ(4u, size) << dst; + LoadFromOffset(kLoadWord, dst.AsCoreRegister(), src_register, src_offset); + } else if (dst.IsRegisterPair()) { + CHECK_EQ(8u, size) << dst; + LoadFromOffset(kLoadWord, dst.AsRegisterPairLow(), src_register, src_offset); + LoadFromOffset(kLoadWord, dst.AsRegisterPairHigh(), src_register, src_offset + 4); + } else if (dst.IsFRegister()) { + LoadSFromOffset(dst.AsFRegister(), src_register, src_offset); + } else { + CHECK(dst.IsDRegister()) << dst; + LoadDFromOffset(dst.AsDRegister(), src_register, src_offset); + } +} + +void MipsAssembler::LoadFromOffset(LoadOperandType type, Register reg, Register base, + int32_t offset) { + switch (type) { + case kLoadSignedByte: + Lb(reg, base, offset); + break; + case kLoadUnsignedByte: + Lbu(reg, base, offset); + break; + case kLoadSignedHalfword: + Lh(reg, base, offset); + break; + case kLoadUnsignedHalfword: + Lhu(reg, base, offset); + break; + case kLoadWord: + Lw(reg, base, offset); + break; + case kLoadWordPair: + LOG(FATAL) << "UNREACHABLE"; + break; + default: + LOG(FATAL) << "UNREACHABLE"; + } +} + +void MipsAssembler::LoadSFromOffset(FRegister reg, Register base, int32_t offset) { + Lwc1(reg, base, offset); +} + +void MipsAssembler::LoadDFromOffset(DRegister reg, Register base, int32_t offset) { + Ldc1(reg, base, offset); +} + +void MipsAssembler::StoreToOffset(StoreOperandType type, Register reg, Register base, + int32_t offset) { + switch (type) { + case kStoreByte: + Sb(reg, base, offset); + break; + case kStoreHalfword: + Sh(reg, base, offset); + break; + case kStoreWord: + Sw(reg, base, offset); + break; + case kStoreWordPair: + LOG(FATAL) << "UNREACHABLE"; + break; + default: + LOG(FATAL) << "UNREACHABLE"; + } +} + +void MipsAssembler::StoreFToOffset(FRegister reg, Register base, int32_t offset) { + Swc1(reg, base, offset); +} + +void MipsAssembler::StoreDToOffset(DRegister reg, Register base, int32_t offset) { + Sdc1(reg, base, offset); +} + +void MipsAssembler::BuildFrame(size_t frame_size, ManagedRegister method_reg, + const std::vector<ManagedRegister>& callee_save_regs, + const std::vector<ManagedRegister>& entry_spills) { + CHECK_ALIGNED(frame_size, kStackAlignment); + + // Increase frame to required size. + IncreaseFrameSize(frame_size); + + // Push callee saves and return address + int stack_offset = frame_size - kPointerSize; + StoreToOffset(kStoreWord, RA, SP, stack_offset); + for (int i = callee_save_regs.size() - 1; i >= 0; --i) { + stack_offset -= kPointerSize; + Register reg = callee_save_regs.at(i).AsMips().AsCoreRegister(); + StoreToOffset(kStoreWord, reg, SP, stack_offset); + } + + // Write out Method*. + StoreToOffset(kStoreWord, method_reg.AsMips().AsCoreRegister(), SP, 0); + + // Write out entry spills. + for (size_t i = 0; i < entry_spills.size(); ++i) { + Register reg = entry_spills.at(i).AsMips().AsCoreRegister(); + StoreToOffset(kStoreWord, reg, SP, frame_size + kPointerSize + (i * kPointerSize)); + } +} + +void MipsAssembler::RemoveFrame(size_t frame_size, + const std::vector<ManagedRegister>& callee_save_regs) { + CHECK_ALIGNED(frame_size, kStackAlignment); + + // Pop callee saves and return address + int stack_offset = frame_size - (callee_save_regs.size() * kPointerSize) - kPointerSize; + for (size_t i = 0; i < callee_save_regs.size(); ++i) { + Register reg = callee_save_regs.at(i).AsMips().AsCoreRegister(); + LoadFromOffset(kLoadWord, reg, SP, stack_offset); + stack_offset += kPointerSize; + } + LoadFromOffset(kLoadWord, RA, SP, stack_offset); + + // Decrease frame to required size. + DecreaseFrameSize(frame_size); +} + +void MipsAssembler::IncreaseFrameSize(size_t adjust) { + CHECK_ALIGNED(adjust, kStackAlignment); + AddConstant(SP, SP, -adjust); +} + +void MipsAssembler::DecreaseFrameSize(size_t adjust) { + CHECK_ALIGNED(adjust, kStackAlignment); + AddConstant(SP, SP, adjust); +} + +void MipsAssembler::Store(FrameOffset dest, ManagedRegister msrc, size_t size) { + MipsManagedRegister src = msrc.AsMips(); + if (src.IsNoRegister()) { + CHECK_EQ(0u, size); + } else if (src.IsCoreRegister()) { + CHECK_EQ(4u, size); + StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); + } else if (src.IsRegisterPair()) { + CHECK_EQ(8u, size); + StoreToOffset(kStoreWord, src.AsRegisterPairLow(), SP, dest.Int32Value()); + StoreToOffset(kStoreWord, src.AsRegisterPairHigh(), + SP, dest.Int32Value() + 4); + } else if (src.IsFRegister()) { + StoreFToOffset(src.AsFRegister(), SP, dest.Int32Value()); + } else { + CHECK(src.IsDRegister()); + StoreDToOffset(src.AsDRegister(), SP, dest.Int32Value()); + } +} + +void MipsAssembler::StoreRef(FrameOffset dest, ManagedRegister msrc) { + MipsManagedRegister src = msrc.AsMips(); + CHECK(src.IsCoreRegister()); + StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); +} + +void MipsAssembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) { + MipsManagedRegister src = msrc.AsMips(); + CHECK(src.IsCoreRegister()); + StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); +} + +void MipsAssembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, + ManagedRegister mscratch) { + MipsManagedRegister scratch = mscratch.AsMips(); + CHECK(scratch.IsCoreRegister()) << scratch; + LoadImmediate(scratch.AsCoreRegister(), imm); + StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value()); +} + +void MipsAssembler::StoreImmediateToThread(ThreadOffset dest, uint32_t imm, + ManagedRegister mscratch) { + MipsManagedRegister scratch = mscratch.AsMips(); + CHECK(scratch.IsCoreRegister()) << scratch; + LoadImmediate(scratch.AsCoreRegister(), imm); + StoreToOffset(kStoreWord, scratch.AsCoreRegister(), S1, dest.Int32Value()); +} + +void MipsAssembler::StoreStackOffsetToThread(ThreadOffset thr_offs, + FrameOffset fr_offs, + ManagedRegister mscratch) { + MipsManagedRegister scratch = mscratch.AsMips(); + CHECK(scratch.IsCoreRegister()) << scratch; + AddConstant(scratch.AsCoreRegister(), SP, fr_offs.Int32Value()); + StoreToOffset(kStoreWord, scratch.AsCoreRegister(), + S1, thr_offs.Int32Value()); +} + +void MipsAssembler::StoreStackPointerToThread(ThreadOffset thr_offs) { + StoreToOffset(kStoreWord, SP, S1, thr_offs.Int32Value()); +} + +void MipsAssembler::StoreSpanning(FrameOffset dest, ManagedRegister msrc, + FrameOffset in_off, ManagedRegister mscratch) { + MipsManagedRegister src = msrc.AsMips(); + MipsManagedRegister scratch = mscratch.AsMips(); + StoreToOffset(kStoreWord, src.AsCoreRegister(), SP, dest.Int32Value()); + LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, in_off.Int32Value()); + StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value() + 4); +} + +void MipsAssembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) { + return EmitLoad(mdest, SP, src.Int32Value(), size); +} + +void MipsAssembler::Load(ManagedRegister mdest, ThreadOffset src, size_t size) { + return EmitLoad(mdest, S1, src.Int32Value(), size); +} + +void MipsAssembler::LoadRef(ManagedRegister mdest, FrameOffset src) { + MipsManagedRegister dest = mdest.AsMips(); + CHECK(dest.IsCoreRegister()); + LoadFromOffset(kLoadWord, dest.AsCoreRegister(), SP, src.Int32Value()); +} + +void MipsAssembler::LoadRef(ManagedRegister mdest, ManagedRegister base, + MemberOffset offs) { + MipsManagedRegister dest = mdest.AsMips(); + CHECK(dest.IsCoreRegister() && dest.IsCoreRegister()); + LoadFromOffset(kLoadWord, dest.AsCoreRegister(), + base.AsMips().AsCoreRegister(), offs.Int32Value()); +} + +void MipsAssembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base, + Offset offs) { + MipsManagedRegister dest = mdest.AsMips(); + CHECK(dest.IsCoreRegister() && dest.IsCoreRegister()) << dest; + LoadFromOffset(kLoadWord, dest.AsCoreRegister(), + base.AsMips().AsCoreRegister(), offs.Int32Value()); +} + +void MipsAssembler::LoadRawPtrFromThread(ManagedRegister mdest, + ThreadOffset offs) { + MipsManagedRegister dest = mdest.AsMips(); + CHECK(dest.IsCoreRegister()); + LoadFromOffset(kLoadWord, dest.AsCoreRegister(), S1, offs.Int32Value()); +} + +void MipsAssembler::SignExtend(ManagedRegister /*mreg*/, size_t /*size*/) { + UNIMPLEMENTED(FATAL) << "no sign extension necessary for mips"; +} + +void MipsAssembler::ZeroExtend(ManagedRegister /*mreg*/, size_t /*size*/) { + UNIMPLEMENTED(FATAL) << "no zero extension necessary for mips"; +} + +void MipsAssembler::Move(ManagedRegister mdest, ManagedRegister msrc, size_t /*size*/) { + MipsManagedRegister dest = mdest.AsMips(); + MipsManagedRegister src = msrc.AsMips(); + if (!dest.Equals(src)) { + if (dest.IsCoreRegister()) { + CHECK(src.IsCoreRegister()) << src; + Move(dest.AsCoreRegister(), src.AsCoreRegister()); + } else if (dest.IsFRegister()) { + CHECK(src.IsFRegister()) << src; + MovS(dest.AsFRegister(), src.AsFRegister()); + } else if (dest.IsDRegister()) { + CHECK(src.IsDRegister()) << src; + MovD(dest.AsDRegister(), src.AsDRegister()); + } else { + CHECK(dest.IsRegisterPair()) << dest; + CHECK(src.IsRegisterPair()) << src; + // Ensure that the first move doesn't clobber the input of the second + if (src.AsRegisterPairHigh() != dest.AsRegisterPairLow()) { + Move(dest.AsRegisterPairLow(), src.AsRegisterPairLow()); + Move(dest.AsRegisterPairHigh(), src.AsRegisterPairHigh()); + } else { + Move(dest.AsRegisterPairHigh(), src.AsRegisterPairHigh()); + Move(dest.AsRegisterPairLow(), src.AsRegisterPairLow()); + } + } + } +} + +void MipsAssembler::CopyRef(FrameOffset dest, FrameOffset src, + ManagedRegister mscratch) { + MipsManagedRegister scratch = mscratch.AsMips(); + CHECK(scratch.IsCoreRegister()) << scratch; + LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value()); + StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value()); +} + +void MipsAssembler::CopyRawPtrFromThread(FrameOffset fr_offs, + ThreadOffset thr_offs, + ManagedRegister mscratch) { + MipsManagedRegister scratch = mscratch.AsMips(); + CHECK(scratch.IsCoreRegister()) << scratch; + LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), + S1, thr_offs.Int32Value()); + StoreToOffset(kStoreWord, scratch.AsCoreRegister(), + SP, fr_offs.Int32Value()); +} + +void MipsAssembler::CopyRawPtrToThread(ThreadOffset thr_offs, + FrameOffset fr_offs, + ManagedRegister mscratch) { + MipsManagedRegister scratch = mscratch.AsMips(); + CHECK(scratch.IsCoreRegister()) << scratch; + LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), + SP, fr_offs.Int32Value()); + StoreToOffset(kStoreWord, scratch.AsCoreRegister(), + S1, thr_offs.Int32Value()); +} + +void MipsAssembler::Copy(FrameOffset dest, FrameOffset src, + ManagedRegister mscratch, size_t size) { + MipsManagedRegister scratch = mscratch.AsMips(); + CHECK(scratch.IsCoreRegister()) << scratch; + CHECK(size == 4 || size == 8) << size; + if (size == 4) { + LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value()); + StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value()); + } else if (size == 8) { + LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value()); + StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value()); + LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, src.Int32Value() + 4); + StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, dest.Int32Value() + 4); + } +} + +void MipsAssembler::Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, + ManagedRegister mscratch, size_t size) { + Register scratch = mscratch.AsMips().AsCoreRegister(); + CHECK_EQ(size, 4u); + LoadFromOffset(kLoadWord, scratch, src_base.AsMips().AsCoreRegister(), src_offset.Int32Value()); + StoreToOffset(kStoreWord, scratch, SP, dest.Int32Value()); +} + +void MipsAssembler::Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, + ManagedRegister mscratch, size_t size) { + Register scratch = mscratch.AsMips().AsCoreRegister(); + CHECK_EQ(size, 4u); + LoadFromOffset(kLoadWord, scratch, SP, src.Int32Value()); + StoreToOffset(kStoreWord, scratch, dest_base.AsMips().AsCoreRegister(), dest_offset.Int32Value()); +} + +void MipsAssembler::Copy(FrameOffset /*dest*/, FrameOffset /*src_base*/, Offset /*src_offset*/, + ManagedRegister /*mscratch*/, size_t /*size*/) { + UNIMPLEMENTED(FATAL) << "no arm implementation"; +#if 0 + Register scratch = mscratch.AsMips().AsCoreRegister(); + CHECK_EQ(size, 4u); + movl(scratch, Address(ESP, src_base)); + movl(scratch, Address(scratch, src_offset)); + movl(Address(ESP, dest), scratch); +#endif +} + +void MipsAssembler::Copy(ManagedRegister dest, Offset dest_offset, + ManagedRegister src, Offset src_offset, + ManagedRegister mscratch, size_t size) { + CHECK_EQ(size, 4u); + Register scratch = mscratch.AsMips().AsCoreRegister(); + LoadFromOffset(kLoadWord, scratch, src.AsMips().AsCoreRegister(), src_offset.Int32Value()); + StoreToOffset(kStoreWord, scratch, dest.AsMips().AsCoreRegister(), dest_offset.Int32Value()); +} + +void MipsAssembler::Copy(FrameOffset /*dest*/, Offset /*dest_offset*/, FrameOffset /*src*/, Offset /*src_offset*/, + ManagedRegister /*mscratch*/, size_t /*size*/) { + UNIMPLEMENTED(FATAL) << "no arm implementation"; +#if 0 + Register scratch = mscratch.AsMips().AsCoreRegister(); + CHECK_EQ(size, 4u); + CHECK_EQ(dest.Int32Value(), src.Int32Value()); + movl(scratch, Address(ESP, src)); + pushl(Address(scratch, src_offset)); + popl(Address(scratch, dest_offset)); +#endif +} + +void MipsAssembler::MemoryBarrier(ManagedRegister) { + UNIMPLEMENTED(FATAL) << "NEEDS TO BE IMPLEMENTED"; +#if 0 +#if ANDROID_SMP != 0 + mfence(); +#endif +#endif +} + +void MipsAssembler::CreateSirtEntry(ManagedRegister mout_reg, + FrameOffset sirt_offset, + ManagedRegister min_reg, bool null_allowed) { + MipsManagedRegister out_reg = mout_reg.AsMips(); + MipsManagedRegister in_reg = min_reg.AsMips(); + CHECK(in_reg.IsNoRegister() || in_reg.IsCoreRegister()) << in_reg; + CHECK(out_reg.IsCoreRegister()) << out_reg; + if (null_allowed) { + Label null_arg; + // Null values get a SIRT entry value of 0. Otherwise, the SIRT entry is + // the address in the SIRT holding the reference. + // e.g. out_reg = (handle == 0) ? 0 : (SP+handle_offset) + if (in_reg.IsNoRegister()) { + LoadFromOffset(kLoadWord, out_reg.AsCoreRegister(), + SP, sirt_offset.Int32Value()); + in_reg = out_reg; + } + if (!out_reg.Equals(in_reg)) { + LoadImmediate(out_reg.AsCoreRegister(), 0); + } + EmitBranch(in_reg.AsCoreRegister(), ZERO, &null_arg, true); + AddConstant(out_reg.AsCoreRegister(), SP, sirt_offset.Int32Value()); + Bind(&null_arg, false); + } else { + AddConstant(out_reg.AsCoreRegister(), SP, sirt_offset.Int32Value()); + } +} + +void MipsAssembler::CreateSirtEntry(FrameOffset out_off, + FrameOffset sirt_offset, + ManagedRegister mscratch, + bool null_allowed) { + MipsManagedRegister scratch = mscratch.AsMips(); + CHECK(scratch.IsCoreRegister()) << scratch; + if (null_allowed) { + Label null_arg; + LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), SP, + sirt_offset.Int32Value()); + // Null values get a SIRT entry value of 0. Otherwise, the sirt entry is + // the address in the SIRT holding the reference. + // e.g. scratch = (scratch == 0) ? 0 : (SP+sirt_offset) + EmitBranch(scratch.AsCoreRegister(), ZERO, &null_arg, true); + AddConstant(scratch.AsCoreRegister(), SP, sirt_offset.Int32Value()); + Bind(&null_arg, false); + } else { + AddConstant(scratch.AsCoreRegister(), SP, sirt_offset.Int32Value()); + } + StoreToOffset(kStoreWord, scratch.AsCoreRegister(), SP, out_off.Int32Value()); +} + +// Given a SIRT entry, load the associated reference. +void MipsAssembler::LoadReferenceFromSirt(ManagedRegister mout_reg, + ManagedRegister min_reg) { + MipsManagedRegister out_reg = mout_reg.AsMips(); + MipsManagedRegister in_reg = min_reg.AsMips(); + CHECK(out_reg.IsCoreRegister()) << out_reg; + CHECK(in_reg.IsCoreRegister()) << in_reg; + Label null_arg; + if (!out_reg.Equals(in_reg)) { + LoadImmediate(out_reg.AsCoreRegister(), 0); + } + EmitBranch(in_reg.AsCoreRegister(), ZERO, &null_arg, true); + LoadFromOffset(kLoadWord, out_reg.AsCoreRegister(), + in_reg.AsCoreRegister(), 0); + Bind(&null_arg, false); +} + +void MipsAssembler::VerifyObject(ManagedRegister /*src*/, bool /*could_be_null*/) { + // TODO: not validating references +} + +void MipsAssembler::VerifyObject(FrameOffset /*src*/, bool /*could_be_null*/) { + // TODO: not validating references +} + +void MipsAssembler::Call(ManagedRegister mbase, Offset offset, ManagedRegister mscratch) { + MipsManagedRegister base = mbase.AsMips(); + MipsManagedRegister scratch = mscratch.AsMips(); + CHECK(base.IsCoreRegister()) << base; + CHECK(scratch.IsCoreRegister()) << scratch; + LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), + base.AsCoreRegister(), offset.Int32Value()); + Jalr(scratch.AsCoreRegister()); + // TODO: place reference map on call +} + +void MipsAssembler::Call(FrameOffset base, Offset offset, ManagedRegister mscratch) { + MipsManagedRegister scratch = mscratch.AsMips(); + CHECK(scratch.IsCoreRegister()) << scratch; + // Call *(*(SP + base) + offset) + LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), + SP, base.Int32Value()); + LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), + scratch.AsCoreRegister(), offset.Int32Value()); + Jalr(scratch.AsCoreRegister()); + // TODO: place reference map on call +} + +void MipsAssembler::Call(ThreadOffset /*offset*/, ManagedRegister /*mscratch*/) { + UNIMPLEMENTED(FATAL) << "no arm implementation"; +#if 0 + fs()->call(Address::Absolute(offset)); +#endif +} + +void MipsAssembler::GetCurrentThread(ManagedRegister tr) { + Move(tr.AsMips().AsCoreRegister(), S1); +} + +void MipsAssembler::GetCurrentThread(FrameOffset offset, + ManagedRegister /*mscratch*/) { + StoreToOffset(kStoreWord, S1, SP, offset.Int32Value()); +} + +void MipsAssembler::SuspendPoll(ManagedRegister /*mscratch*/, + ManagedRegister /*return_reg*/, + FrameOffset /*return_save_location*/, + size_t /*return_size*/) { + UNIMPLEMENTED(FATAL) << "NEEDS TO BE IMPLEMENTED"; +#if 0 + MipsSuspendCountSlowPath* slow = + new MipsSuspendCountSlowPath(return_reg.AsMips(), return_save_location, + return_size); + buffer_.EnqueueSlowPath(slow); + fs()->cmpl(Address::Absolute(Thread::SuspendCountOffset()), Immediate(0)); + j(kNotEqual, slow->Entry()); + Bind(slow->Continuation()); +#endif +} + +void MipsSuspendCountSlowPath::Emit(Assembler* sasm) { + MipsAssembler* sp_asm = down_cast<MipsAssembler*>(sasm); +#define __ sp_asm-> + __ Bind(&entry_, true); + // Save return value + __ Store(return_save_location_, return_register_, return_size_); + // Pass Thread::Current as argument and call pCheckSuspendFromCode + __ Move(A0, S1); + __ LoadFromOffset(kLoadWord, T9, S1, ENTRYPOINT_OFFSET(pCheckSuspendFromCode)); + __ Jalr(T9); + // Reload return value + __ Load(return_register_, return_save_location_, return_size_); + __ EmitJump(&continuation_, false); +#undef __ +} + +void MipsAssembler::ExceptionPoll(ManagedRegister mscratch, size_t stack_adjust) { + MipsManagedRegister scratch = mscratch.AsMips(); + MipsExceptionSlowPath* slow = new MipsExceptionSlowPath(scratch, stack_adjust); + buffer_.EnqueueSlowPath(slow); + LoadFromOffset(kLoadWord, scratch.AsCoreRegister(), + S1, Thread::ExceptionOffset().Int32Value()); + EmitBranch(scratch.AsCoreRegister(), ZERO, slow->Entry(), false); +} + +void MipsExceptionSlowPath::Emit(Assembler* sasm) { + MipsAssembler* sp_asm = down_cast<MipsAssembler*>(sasm); +#define __ sp_asm-> + __ Bind(&entry_, false); + if (stack_adjust_ != 0) { // Fix up the frame. + __ DecreaseFrameSize(stack_adjust_); + } + // Pass exception object as argument + // Don't care about preserving A0 as this call won't return + __ Move(A0, scratch_.AsCoreRegister()); + // Set up call to Thread::Current()->pDeliverException + __ LoadFromOffset(kLoadWord, T9, S1, ENTRYPOINT_OFFSET(pDeliverException)); + __ Jr(T9); + // Call never returns + __ Break(); +#undef __ +} + +} // namespace mips +} // namespace art diff --git a/src/oat/utils/mips/assembler_mips.h b/src/oat/utils/mips/assembler_mips.h new file mode 100644 index 0000000000..ae81fa7080 --- /dev/null +++ b/src/oat/utils/mips/assembler_mips.h @@ -0,0 +1,535 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_SRC_OAT_UTILS_MIPS_ASSEMBLER_MIPS_H_ +#define ART_SRC_OAT_UTILS_MIPS_ASSEMBLER_MIPS_H_ + +#include <vector> +#include "constants_mips.h" +#include "globals.h" +#include "managed_register_mips.h" +#include "macros.h" +#include "oat/utils/assembler.h" +#include "offsets.h" +#include "utils.h" + +namespace art { +namespace mips { +#if 0 +class Operand { + public: + uint8_t mod() const { + return (encoding_at(0) >> 6) & 3; + } + + Register rm() const { + return static_cast<Register>(encoding_at(0) & 7); + } + + ScaleFactor scale() const { + return static_cast<ScaleFactor>((encoding_at(1) >> 6) & 3); + } + + Register index() const { + return static_cast<Register>((encoding_at(1) >> 3) & 7); + } + + Register base() const { + return static_cast<Register>(encoding_at(1) & 7); + } + + int8_t disp8() const { + CHECK_GE(length_, 2); + return static_cast<int8_t>(encoding_[length_ - 1]); + } + + int32_t disp32() const { + CHECK_GE(length_, 5); + int32_t value; + memcpy(&value, &encoding_[length_ - 4], sizeof(value)); + return value; + } + + bool IsRegister(Register reg) const { + return ((encoding_[0] & 0xF8) == 0xC0) // Addressing mode is register only. + && ((encoding_[0] & 0x07) == reg); // Register codes match. + } + + protected: + // Operand can be sub classed (e.g: Address). + Operand() : length_(0) { } + + void SetModRM(int mod, Register rm) { + CHECK_EQ(mod & ~3, 0); + encoding_[0] = (mod << 6) | rm; + length_ = 1; + } + + void SetSIB(ScaleFactor scale, Register index, Register base) { + CHECK_EQ(length_, 1); + CHECK_EQ(scale & ~3, 0); + encoding_[1] = (scale << 6) | (index << 3) | base; + length_ = 2; + } + + void SetDisp8(int8_t disp) { + CHECK(length_ == 1 || length_ == 2); + encoding_[length_++] = static_cast<uint8_t>(disp); + } + + void SetDisp32(int32_t disp) { + CHECK(length_ == 1 || length_ == 2); + int disp_size = sizeof(disp); + memmove(&encoding_[length_], &disp, disp_size); + length_ += disp_size; + } + + private: + byte length_; + byte encoding_[6]; + byte padding_; + + explicit Operand(Register reg) { SetModRM(3, reg); } + + // Get the operand encoding byte at the given index. + uint8_t encoding_at(int index) const { + CHECK_GE(index, 0); + CHECK_LT(index, length_); + return encoding_[index]; + } + + friend class MipsAssembler; + + // TODO: Remove the #if when Mac OS build server no longer uses GCC 4.2.*. +#if GCC_VERSION >= 40300 + DISALLOW_COPY_AND_ASSIGN(Operand); +#endif +}; + + +class Address : public Operand { + public: + Address(Register base, int32_t disp) { + Init(base, disp); + } + + Address(Register base, Offset disp) { + Init(base, disp.Int32Value()); + } + + Address(Register base, FrameOffset disp) { + CHECK_EQ(base, ESP); + Init(ESP, disp.Int32Value()); + } + + Address(Register base, MemberOffset disp) { + Init(base, disp.Int32Value()); + } + + void Init(Register base, int32_t disp) { + if (disp == 0 && base != EBP) { + SetModRM(0, base); + if (base == ESP) SetSIB(TIMES_1, ESP, base); + } else if (disp >= -128 && disp <= 127) { + SetModRM(1, base); + if (base == ESP) SetSIB(TIMES_1, ESP, base); + SetDisp8(disp); + } else { + SetModRM(2, base); + if (base == ESP) SetSIB(TIMES_1, ESP, base); + SetDisp32(disp); + } + } + + + Address(Register index, ScaleFactor scale, int32_t disp) { + CHECK_NE(index, ESP); // Illegal addressing mode. + SetModRM(0, ESP); + SetSIB(scale, index, EBP); + SetDisp32(disp); + } + + Address(Register base, Register index, ScaleFactor scale, int32_t disp) { + CHECK_NE(index, ESP); // Illegal addressing mode. + if (disp == 0 && base != EBP) { + SetModRM(0, ESP); + SetSIB(scale, index, base); + } else if (disp >= -128 && disp <= 127) { + SetModRM(1, ESP); + SetSIB(scale, index, base); + SetDisp8(disp); + } else { + SetModRM(2, ESP); + SetSIB(scale, index, base); + SetDisp32(disp); + } + } + + static Address Absolute(uword addr) { + Address result; + result.SetModRM(0, EBP); + result.SetDisp32(addr); + return result; + } + + static Address Absolute(ThreadOffset addr) { + return Absolute(addr.Int32Value()); + } + + private: + Address() {} + + // TODO: Remove the #if when Mac OS build server no longer uses GCC 4.2.*. +#if GCC_VERSION >= 40300 + DISALLOW_COPY_AND_ASSIGN(Address); +#endif +}; + +#endif + +enum LoadOperandType { + kLoadSignedByte, + kLoadUnsignedByte, + kLoadSignedHalfword, + kLoadUnsignedHalfword, + kLoadWord, + kLoadWordPair, + kLoadSWord, + kLoadDWord +}; + +enum StoreOperandType { + kStoreByte, + kStoreHalfword, + kStoreWord, + kStoreWordPair, + kStoreSWord, + kStoreDWord +}; + +class MipsAssembler : public Assembler { + public: + MipsAssembler() {} + virtual ~MipsAssembler() {} + + // Emit Machine Instructions. + void Add(Register rd, Register rs, Register rt); + void Addu(Register rd, Register rs, Register rt); + void Addi(Register rt, Register rs, uint16_t imm16); + void Addiu(Register rt, Register rs, uint16_t imm16); + void Sub(Register rd, Register rs, Register rt); + void Subu(Register rd, Register rs, Register rt); + void Mult(Register rs, Register rt); + void Multu(Register rs, Register rt); + void Div(Register rs, Register rt); + void Divu(Register rs, Register rt); + + void And(Register rd, Register rs, Register rt); + void Andi(Register rt, Register rs, uint16_t imm16); + void Or(Register rd, Register rs, Register rt); + void Ori(Register rt, Register rs, uint16_t imm16); + void Xor(Register rd, Register rs, Register rt); + void Xori(Register rt, Register rs, uint16_t imm16); + void Nor(Register rd, Register rs, Register rt); + + void Sll(Register rd, Register rs, int shamt); + void Srl(Register rd, Register rs, int shamt); + void Sra(Register rd, Register rs, int shamt); + void Sllv(Register rd, Register rs, Register rt); + void Srlv(Register rd, Register rs, Register rt); + void Srav(Register rd, Register rs, Register rt); + + void Lb(Register rt, Register rs, uint16_t imm16); + void Lh(Register rt, Register rs, uint16_t imm16); + void Lw(Register rt, Register rs, uint16_t imm16); + void Lbu(Register rt, Register rs, uint16_t imm16); + void Lhu(Register rt, Register rs, uint16_t imm16); + void Lui(Register rt, uint16_t imm16); + void Mfhi(Register rd); + void Mflo(Register rd); + + void Sb(Register rt, Register rs, uint16_t imm16); + void Sh(Register rt, Register rs, uint16_t imm16); + void Sw(Register rt, Register rs, uint16_t imm16); + + void Slt(Register rd, Register rs, Register rt); + void Sltu(Register rd, Register rs, Register rt); + void Slti(Register rt, Register rs, uint16_t imm16); + void Sltiu(Register rt, Register rs, uint16_t imm16); + + void Beq(Register rt, Register rs, uint16_t imm16); + void Bne(Register rt, Register rs, uint16_t imm16); + void J(uint32_t address); + void Jal(uint32_t address); + void Jr(Register rs); + void Jalr(Register rs); + + void AddS(FRegister fd, FRegister fs, FRegister ft); + void SubS(FRegister fd, FRegister fs, FRegister ft); + void MulS(FRegister fd, FRegister fs, FRegister ft); + void DivS(FRegister fd, FRegister fs, FRegister ft); + void AddD(DRegister fd, DRegister fs, DRegister ft); + void SubD(DRegister fd, DRegister fs, DRegister ft); + void MulD(DRegister fd, DRegister fs, DRegister ft); + void DivD(DRegister fd, DRegister fs, DRegister ft); + void MovS(FRegister fd, FRegister fs); + void MovD(DRegister fd, DRegister fs); + + void Mfc1(Register rt, FRegister fs); + void Mtc1(FRegister ft, Register rs); + void Lwc1(FRegister ft, Register rs, uint16_t imm16); + void Ldc1(DRegister ft, Register rs, uint16_t imm16); + void Swc1(FRegister ft, Register rs, uint16_t imm16); + void Sdc1(DRegister ft, Register rs, uint16_t imm16); + + void Break(); + void Move(Register rt, Register rs); + void Clear(Register rt); + void Not(Register rt, Register rs); + void Mul(Register rd, Register rs, Register rt); + void Div(Register rd, Register rs, Register rt); + void Rem(Register rd, Register rs, Register rt); + + void AddConstant(Register rt, Register rs, int32_t value); + void LoadImmediate(Register rt, int32_t value); + + void EmitLoad(ManagedRegister m_dst, Register src_register, int32_t src_offset, size_t size); + void LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset); + void LoadSFromOffset(FRegister reg, Register base, int32_t offset); + void LoadDFromOffset(DRegister reg, Register base, int32_t offset); + void StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset); + void StoreFToOffset(FRegister reg, Register base, int32_t offset); + void StoreDToOffset(DRegister reg, Register base, int32_t offset); + +#if 0 + MipsAssembler* lock(); + + void mfence(); + + MipsAssembler* fs(); + + // + // Macros for High-level operations. + // + + void AddImmediate(Register reg, const Immediate& imm); + + void LoadDoubleConstant(XmmRegister dst, double value); + + void DoubleNegate(XmmRegister d); + void FloatNegate(XmmRegister f); + + void DoubleAbs(XmmRegister reg); + + void LockCmpxchgl(const Address& address, Register reg) { + lock()->cmpxchgl(address, reg); + } + + // + // Misc. functionality + // + int PreferredLoopAlignment() { return 16; } + void Align(int alignment, int offset); + + // Debugging and bringup support. + void Stop(const char* message); +#endif + + // Emit data (e.g. encoded instruction or immediate) to the instruction stream. + void Emit(int32_t value); + void EmitBranch(Register rt, Register rs, Label* label, bool equal); + void EmitJump(Label* label, bool link); + void Bind(Label* label, bool is_jump); + + // + // Overridden common assembler high-level functionality + // + + // Emit code that will create an activation on the stack + virtual void BuildFrame(size_t frame_size, ManagedRegister method_reg, + const std::vector<ManagedRegister>& callee_save_regs, + const std::vector<ManagedRegister>& entry_spills); + + // Emit code that will remove an activation from the stack + virtual void RemoveFrame(size_t frame_size, + const std::vector<ManagedRegister>& callee_save_regs); + + virtual void IncreaseFrameSize(size_t adjust); + virtual void DecreaseFrameSize(size_t adjust); + + // Store routines + virtual void Store(FrameOffset offs, ManagedRegister msrc, size_t size); + virtual void StoreRef(FrameOffset dest, ManagedRegister msrc); + virtual void StoreRawPtr(FrameOffset dest, ManagedRegister msrc); + + virtual void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, + ManagedRegister mscratch); + + virtual void StoreImmediateToThread(ThreadOffset dest, uint32_t imm, + ManagedRegister mscratch); + + virtual void StoreStackOffsetToThread(ThreadOffset thr_offs, + FrameOffset fr_offs, + ManagedRegister mscratch); + + virtual void StoreStackPointerToThread(ThreadOffset thr_offs); + + virtual void StoreSpanning(FrameOffset dest, ManagedRegister msrc, + FrameOffset in_off, ManagedRegister mscratch); + + // Load routines + virtual void Load(ManagedRegister mdest, FrameOffset src, size_t size); + + virtual void Load(ManagedRegister mdest, ThreadOffset src, size_t size); + + virtual void LoadRef(ManagedRegister dest, FrameOffset src); + + virtual void LoadRef(ManagedRegister mdest, ManagedRegister base, + MemberOffset offs); + + virtual void LoadRawPtr(ManagedRegister mdest, ManagedRegister base, + Offset offs); + + virtual void LoadRawPtrFromThread(ManagedRegister mdest, + ThreadOffset offs); + + // Copying routines + virtual void Move(ManagedRegister mdest, ManagedRegister msrc, size_t size); + + virtual void CopyRawPtrFromThread(FrameOffset fr_offs, ThreadOffset thr_offs, + ManagedRegister mscratch); + + virtual void CopyRawPtrToThread(ThreadOffset thr_offs, FrameOffset fr_offs, + ManagedRegister mscratch); + + virtual void CopyRef(FrameOffset dest, FrameOffset src, + ManagedRegister mscratch); + + virtual void Copy(FrameOffset dest, FrameOffset src, ManagedRegister mscratch, size_t size); + + virtual void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, + ManagedRegister mscratch, size_t size); + + virtual void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, + ManagedRegister mscratch, size_t size); + + virtual void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, + ManagedRegister mscratch, size_t size); + + virtual void Copy(ManagedRegister dest, Offset dest_offset, + ManagedRegister src, Offset src_offset, + ManagedRegister mscratch, size_t size); + + virtual void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset, + ManagedRegister mscratch, size_t size); + + virtual void MemoryBarrier(ManagedRegister); + + // Sign extension + virtual void SignExtend(ManagedRegister mreg, size_t size); + + // Zero extension + virtual void ZeroExtend(ManagedRegister mreg, size_t size); + + // Exploit fast access in managed code to Thread::Current() + virtual void GetCurrentThread(ManagedRegister tr); + virtual void GetCurrentThread(FrameOffset dest_offset, + ManagedRegister mscratch); + + // Set up out_reg to hold a Object** into the SIRT, or to be NULL if the + // value is null and null_allowed. in_reg holds a possibly stale reference + // that can be used to avoid loading the SIRT entry to see if the value is + // NULL. + virtual void CreateSirtEntry(ManagedRegister out_reg, FrameOffset sirt_offset, + ManagedRegister in_reg, bool null_allowed); + + // Set up out_off to hold a Object** into the SIRT, or to be NULL if the + // value is null and null_allowed. + virtual void CreateSirtEntry(FrameOffset out_off, FrameOffset sirt_offset, + ManagedRegister mscratch, bool null_allowed); + + // src holds a SIRT entry (Object**) load this into dst + virtual void LoadReferenceFromSirt(ManagedRegister dst, + ManagedRegister src); + + // Heap::VerifyObject on src. In some cases (such as a reference to this) we + // know that src may not be null. + virtual void VerifyObject(ManagedRegister src, bool could_be_null); + virtual void VerifyObject(FrameOffset src, bool could_be_null); + + // Call to address held at [base+offset] + virtual void Call(ManagedRegister base, Offset offset, + ManagedRegister mscratch); + virtual void Call(FrameOffset base, Offset offset, + ManagedRegister mscratch); + virtual void Call(ThreadOffset offset, ManagedRegister mscratch); + + // Generate code to check if Thread::Current()->suspend_count_ is non-zero + // and branch to a SuspendSlowPath if it is. The SuspendSlowPath will continue + // at the next instruction. + virtual void SuspendPoll(ManagedRegister mscratch, ManagedRegister return_reg, + FrameOffset return_save_location, + size_t return_size); + + // Generate code to check if Thread::Current()->exception_ is non-null + // and branch to a ExceptionSlowPath if it is. + virtual void ExceptionPoll(ManagedRegister mscratch, size_t stack_adjust); + + private: + void EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct); + void EmitI(int opcode, Register rs, Register rt, uint16_t imm); + void EmitJ(int opcode, int address); + void EmitFR(int opcode, int fmt, FRegister ft, FRegister fs, FRegister fd, int funct); + void EmitFI(int opcode, int fmt, FRegister rt, uint16_t imm); + + int32_t EncodeBranchOffset(int offset, int32_t inst, bool is_jump); + int DecodeBranchOffset(int32_t inst, bool is_jump); + + DISALLOW_COPY_AND_ASSIGN(MipsAssembler); +}; + +// Slowpath entered when Thread::Current()->_exception is non-null +class MipsExceptionSlowPath : public SlowPath { + public: + explicit MipsExceptionSlowPath(MipsManagedRegister scratch, size_t stack_adjust) + : scratch_(scratch), stack_adjust_(stack_adjust) {} + virtual void Emit(Assembler *sp_asm); + private: + const MipsManagedRegister scratch_; + const size_t stack_adjust_; +}; + +// Slowpath entered when Thread::Current()->_suspend_count is non-zero +class MipsSuspendCountSlowPath : public SlowPath { + public: + MipsSuspendCountSlowPath(MipsManagedRegister return_reg, + FrameOffset return_save_location, + size_t return_size) + : return_register_(return_reg), return_save_location_(return_save_location), + return_size_(return_size) {} + virtual void Emit(Assembler *sp_asm); + + private: + // Remember how to save the return value + const MipsManagedRegister return_register_; + const FrameOffset return_save_location_; + const size_t return_size_; +}; + +} // namespace mips +} // namespace art + +#endif // ART_SRC_OAT_UTILS_MIPS_ASSEMBLER_MIPS_H_ diff --git a/src/oat/utils/mips/managed_register_mips.cc b/src/oat/utils/mips/managed_register_mips.cc new file mode 100644 index 0000000000..b48c959653 --- /dev/null +++ b/src/oat/utils/mips/managed_register_mips.cc @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "managed_register_mips.h" + +#include "globals.h" + +namespace art { +namespace mips { + +// These core registers are never available for allocation. +static const Register kReservedCoreRegistersArray[] = { S0, S1 }; + +// We need all registers for caching. +static const int kNumberOfAvailableCoreRegisters = (S7 - T0) + 1; +static const int kNumberOfAvailableFRegisters = kNumberOfFRegisters; +static const int kNumberOfAvailableDRegisters = kNumberOfDRegisters; +static const int kNumberOfAvailableOverlappingDRegisters = + kNumberOfOverlappingDRegisters; +static const int kNumberOfAvailableRegisterPairs = kNumberOfRegisterPairs; + +bool MipsManagedRegister::Overlaps(const MipsManagedRegister& other) const { + if (IsNoRegister() || other.IsNoRegister()) return false; + CHECK(IsValidManagedRegister()); + CHECK(other.IsValidManagedRegister()); + if (Equals(other)) return true; + if (IsRegisterPair()) { + Register low = AsRegisterPairLow(); + Register high = AsRegisterPairHigh(); + return MipsManagedRegister::FromCoreRegister(low).Overlaps(other) || + MipsManagedRegister::FromCoreRegister(high).Overlaps(other); + } + if (IsOverlappingDRegister()) { + if (other.IsDRegister()) return Equals(other); + if (other.IsFRegister()) { + FRegister low = AsOverlappingDRegisterLow(); + FRegister high = AsOverlappingDRegisterHigh(); + FRegister other_freg = other.AsFRegister(); + return (low == other_freg) || (high == other_freg); + } + return false; + } + if (other.IsRegisterPair() || other.IsOverlappingDRegister()) { + return other.Overlaps(*this); + } + return false; +} + + +int MipsManagedRegister::AllocIdLow() const { + CHECK(IsOverlappingDRegister() || IsRegisterPair()); + const int r = RegId() - (kNumberOfCoreRegIds + kNumberOfFRegIds); + int low; + if (r < kNumberOfOverlappingDRegIds) { + CHECK(IsOverlappingDRegister()); + low = (r * 2) + kNumberOfCoreRegIds; // Return an FRegister. + } else { + CHECK(IsRegisterPair()); + low = (r - kNumberOfDRegIds) * 2; // Return a Register. + if (low > 24) { + // we got a pair higher than T8_T9, must be the dalvik special case + low = 5; + } + } + return low; +} + + +int MipsManagedRegister::AllocIdHigh() const { + return AllocIdLow() + 1; +} + + +void MipsManagedRegister::Print(std::ostream& os) const { + if (!IsValidManagedRegister()) { + os << "No Register"; + } else if (IsCoreRegister()) { + os << "Core: " << static_cast<int>(AsCoreRegister()); + } else if (IsRegisterPair()) { + os << "Pair: " << AsRegisterPairLow() << ", " << AsRegisterPairHigh(); + } else if (IsFRegister()) { + os << "FRegister: " << static_cast<int>(AsFRegister()); + } else if (IsDRegister()) { + os << "DRegister: " << static_cast<int>(AsDRegister()); + } else { + os << "??: " << RegId(); + } +} + +std::ostream& operator<<(std::ostream& os, const MipsManagedRegister& reg) { + reg.Print(os); + return os; +} + +std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { + os << MipsManagedRegister::FromRegisterPair(reg); + return os; +} + +} // namespace mips +} // namespace art diff --git a/src/oat/utils/mips/managed_register_mips.h b/src/oat/utils/mips/managed_register_mips.h new file mode 100644 index 0000000000..aaaabfcc0c --- /dev/null +++ b/src/oat/utils/mips/managed_register_mips.h @@ -0,0 +1,228 @@ +/* + * Copyright (C) 2011 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_SRC_OAT_UTILS_MIPS_MANAGED_REGISTER_MIPS_H_ +#define ART_SRC_OAT_UTILS_MIPS_MANAGED_REGISTER_MIPS_H_ + +#include "constants_mips.h" +#include "oat/utils/managed_register.h" + +namespace art { +namespace mips { + +// Values for register pairs. +enum RegisterPair { + V0_V1 = 0, + A0_A1 = 1, + A2_A3 = 2, + T0_T1 = 3, + T2_T3 = 4, + T4_T5 = 5, + T6_T7 = 6, + S0_S1 = 7, + S2_S3 = 8, + S4_S5 = 9, + S6_S7 = 10, + A1_A2 = 11, // Dalvik style passing + kNumberOfRegisterPairs = 12, + kNoRegisterPair = -1, +}; + +std::ostream& operator<<(std::ostream& os, const RegisterPair& reg); + +const int kNumberOfCoreRegIds = kNumberOfCoreRegisters; +const int kNumberOfCoreAllocIds = kNumberOfCoreRegisters; + +const int kNumberOfFRegIds = kNumberOfFRegisters; +const int kNumberOfFAllocIds = kNumberOfFRegisters; + +const int kNumberOfDRegIds = kNumberOfDRegisters; +const int kNumberOfOverlappingDRegIds = kNumberOfOverlappingDRegisters; +const int kNumberOfDAllocIds = kNumberOfDRegisters; + +const int kNumberOfPairRegIds = kNumberOfRegisterPairs; + +const int kNumberOfRegIds = kNumberOfCoreRegIds + kNumberOfFRegIds + + kNumberOfDRegIds + kNumberOfPairRegIds; +const int kNumberOfAllocIds = + kNumberOfCoreAllocIds + kNumberOfFAllocIds + kNumberOfDAllocIds; + +// Register ids map: +// [0..R[ core registers (enum Register) +// [R..F[ single precision FP registers (enum FRegister) +// [F..D[ double precision FP registers (enum DRegister) +// [D..P[ core register pairs (enum RegisterPair) +// where +// R = kNumberOfCoreRegIds +// F = R + kNumberOfFRegIds +// D = F + kNumberOfDRegIds +// P = D + kNumberOfRegisterPairs + +// Allocation ids map: +// [0..R[ core registers (enum Register) +// [R..F[ single precision FP registers (enum FRegister) +// where +// R = kNumberOfCoreRegIds +// F = R + kNumberOfFRegIds + + +// An instance of class 'ManagedRegister' represents a single core register (enum +// Register), a single precision FP register (enum FRegister), a double precision +// FP register (enum DRegister), or a pair of core registers (enum RegisterPair). +// 'ManagedRegister::NoRegister()' provides an invalid register. +// There is a one-to-one mapping between ManagedRegister and register id. +class MipsManagedRegister : public ManagedRegister { + public: + Register AsCoreRegister() const { + CHECK(IsCoreRegister()); + return static_cast<Register>(id_); + } + + FRegister AsFRegister() const { + CHECK(IsFRegister()); + return static_cast<FRegister>(id_ - kNumberOfCoreRegIds); + } + + DRegister AsDRegister() const { + CHECK(IsDRegister()); + return static_cast<DRegister>(id_ - kNumberOfCoreRegIds - kNumberOfFRegIds); + } + + FRegister AsOverlappingDRegisterLow() const { + CHECK(IsOverlappingDRegister()); + DRegister d_reg = AsDRegister(); + return static_cast<FRegister>(d_reg * 2); + } + + FRegister AsOverlappingDRegisterHigh() const { + CHECK(IsOverlappingDRegister()); + DRegister d_reg = AsDRegister(); + return static_cast<FRegister>(d_reg * 2 + 1); + } + + Register AsRegisterPairLow() const { + CHECK(IsRegisterPair()); + // Appropriate mapping of register ids allows to use AllocIdLow(). + return FromRegId(AllocIdLow()).AsCoreRegister(); + } + + Register AsRegisterPairHigh() const { + CHECK(IsRegisterPair()); + // Appropriate mapping of register ids allows to use AllocIdHigh(). + return FromRegId(AllocIdHigh()).AsCoreRegister(); + } + + bool IsCoreRegister() const { + CHECK(IsValidManagedRegister()); + return (0 <= id_) && (id_ < kNumberOfCoreRegIds); + } + + bool IsFRegister() const { + CHECK(IsValidManagedRegister()); + const int test = id_ - kNumberOfCoreRegIds; + return (0 <= test) && (test < kNumberOfFRegIds); + } + + bool IsDRegister() const { + CHECK(IsValidManagedRegister()); + const int test = id_ - (kNumberOfCoreRegIds + kNumberOfFRegIds); + return (0 <= test) && (test < kNumberOfDRegIds); + } + + // Returns true if this DRegister overlaps FRegisters. + bool IsOverlappingDRegister() const { + CHECK(IsValidManagedRegister()); + const int test = id_ - (kNumberOfCoreRegIds + kNumberOfFRegIds); + return (0 <= test) && (test < kNumberOfOverlappingDRegIds); + } + + bool IsRegisterPair() const { + CHECK(IsValidManagedRegister()); + const int test = + id_ - (kNumberOfCoreRegIds + kNumberOfFRegIds + kNumberOfDRegIds); + return (0 <= test) && (test < kNumberOfPairRegIds); + } + + void Print(std::ostream& os) const; + + // Returns true if the two managed-registers ('this' and 'other') overlap. + // Either managed-register may be the NoRegister. If both are the NoRegister + // then false is returned. + bool Overlaps(const MipsManagedRegister& other) const; + + static MipsManagedRegister FromCoreRegister(Register r) { + CHECK_NE(r, kNoRegister); + return FromRegId(r); + } + + static MipsManagedRegister FromFRegister(FRegister r) { + CHECK_NE(r, kNoFRegister); + return FromRegId(r + kNumberOfCoreRegIds); + } + + static MipsManagedRegister FromDRegister(DRegister r) { + CHECK_NE(r, kNoDRegister); + return FromRegId(r + kNumberOfCoreRegIds + kNumberOfFRegIds); + } + + static MipsManagedRegister FromRegisterPair(RegisterPair r) { + CHECK_NE(r, kNoRegisterPair); + return FromRegId(r + (kNumberOfCoreRegIds + kNumberOfFRegIds + kNumberOfDRegIds)); + } + + private: + bool IsValidManagedRegister() const { + return (0 <= id_) && (id_ < kNumberOfRegIds); + } + + int RegId() const { + CHECK(!IsNoRegister()); + return id_; + } + + int AllocId() const { + CHECK(IsValidManagedRegister() && !IsOverlappingDRegister() && !IsRegisterPair()); + CHECK_LT(id_, kNumberOfAllocIds); + return id_; + } + + int AllocIdLow() const; + int AllocIdHigh() const; + + friend class ManagedRegister; + + explicit MipsManagedRegister(int reg_id) : ManagedRegister(reg_id) {} + + static MipsManagedRegister FromRegId(int reg_id) { + MipsManagedRegister reg(reg_id); + CHECK(reg.IsValidManagedRegister()); + return reg; + } +}; + +std::ostream& operator<<(std::ostream& os, const MipsManagedRegister& reg); + +} // namespace mips + +inline mips::MipsManagedRegister ManagedRegister::AsMips() const { + mips::MipsManagedRegister reg(id_); + CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister()); + return reg; +} + +} // namespace art + +#endif // ART_SRC_OAT_UTILS_MIPS_MANAGED_REGISTER_MIPS_H_ diff --git a/src/runtime.cc b/src/runtime.cc index 60cc6f576c..89477b0484 100644 --- a/src/runtime.cc +++ b/src/runtime.cc @@ -27,6 +27,7 @@ #include "class_linker.h" #include "class_loader.h" #include "constants_arm.h" +#include "constants_mips.h" #include "constants_x86.h" #include "debugger.h" #include "heap.h" @@ -1003,6 +1004,32 @@ Method* Runtime::CreateCalleeSaveMethod(InstructionSet instruction_set, CalleeSa method->SetFrameSizeInBytes(frame_size); method->SetCoreSpillMask(core_spills); method->SetFpSpillMask(fp_spills); + } else if (instruction_set == kMips) { + uint32_t ref_spills = (1 << art::mips::S2) | (1 << art::mips::S3) | (1 << art::mips::S4) | + (1 << art::mips::S5) | (1 << art::mips::S6) | (1 << art::mips::S7) | + (1 << art::mips::FP); + uint32_t arg_spills = (1 << art::mips::A1) | (1 << art::mips::A2) | (1 << art::mips::A3); + uint32_t all_spills = (1 << art::mips::S1) | (1 << art::mips::SP); + uint32_t core_spills = ref_spills | (type == kRefsAndArgs ? arg_spills : 0) | + (type == kSaveAll ? all_spills : 0) | (1 << art::mips::RA); + uint32_t fp_all_spills = (1 << art::mips::F0) | (1 << art::mips::F1) | (1 << art::mips::F2) | + (1 << art::mips::F3) | (1 << art::mips::F4) | (1 << art::mips::F5) | + (1 << art::mips::F6) | (1 << art::mips::F7) | (1 << art::mips::F8) | + (1 << art::mips::F9) | (1 << art::mips::F10) | (1 << art::mips::F11) | + (1 << art::mips::F12) | (1 << art::mips::F13) | (1 << art::mips::F14) | + (1 << art::mips::F15) | (1 << art::mips::F16) | (1 << art::mips::F17) | + (1 << art::mips::F18) | (1 << art::mips::F19) | (1 << art::mips::F20) | + (1 << art::mips::F21) | (1 << art::mips::F22) | (1 << art::mips::F23) | + (1 << art::mips::F24) | (1 << art::mips::F25) | (1 << art::mips::F26) | + (1 << art::mips::F27) | (1 << art::mips::F28) | (1 << art::mips::F29) | + (1 << art::mips::F30) | (1 << art::mips::F31); + uint32_t fp_spills = type == kSaveAll ? fp_all_spills : 0; + size_t frame_size = RoundUp((__builtin_popcount(core_spills) /* gprs */ + + __builtin_popcount(fp_spills) /* fprs */ + + 1 /* Method* */) * kPointerSize, kStackAlignment); + method->SetFrameSizeInBytes(frame_size); + method->SetCoreSpillMask(core_spills); + method->SetFpSpillMask(fp_spills); } else if (instruction_set == kX86) { uint32_t ref_spills = (1 << art::x86::EBP) | (1 << art::x86::ESI) | (1 << art::x86::EDI); uint32_t arg_spills = (1 << art::x86::ECX) | (1 << art::x86::EDX) | (1 << art::x86::EBX); |